SIPC42S2N08 Datasheet, PDF (1/5 Pages) Infineon Technologies AG – OptiMOS Chip data sheet

OptiMOS^â Chip data sheet
Preliminary data
SIPC42S2N08
Feature
• N-Channel
• Enhancement mode
• 175°C operating temperature
• Avalanche rated
• dv/dt rated
• Integrated gate resistance
for easy parallel connection
V_DS
R_DS(on)
Die size
Thickness
75
4.2
7x6
175
V
mΩ
mm²
µm
Ordering Code
unsawn wafer on foil
sawn wafer on foil
surf tape
on request
Q67061-S7146
on request
DESCRIPTION
• Assembly by epoxy die bonding or soldering
• AQL 1.5 for visual inspection according to failure catalog A67207-A7001-A001 issue C
on 100% measured wafer
• Storage of chips and wafer according technical guideline 14 Doc. No. A66003-R14-T1-B-35
Maximum Ratings, at T_j = 25 °C, unless otherwise specified
Parameter
Symbol
Continuous drain current ¹⁾²⁾
I_D
T_C=25°C
Avalanche energy, single pulse¹⁾
E_AS
I_D=80A, V_DD=25V, R_GS=25Ω
Repetitive avalanche energy, limited by T_jmax ¹⁾²⁾ E_AR
Gate source voltage
V_GS
Additional gate resistance
R_G
Operating and storage temperature
T_j , T_stg
1Defined _{by design. Not subject to production test.}
2Calculated _{with RthJC = 0.3 K/W}
Infineon AG, AI AP APE, Informations #184R
1
Value
Unit
227
A
1070
mJ
50
mJ
±20
V
5 ±20%
Ω
-55... +175
°C
2002-02-01