SEMD12 Datasheet, PDF (1/5 Pages) Infineon Technologies AG – NPN/PNP Silicon Digital Transistor Array Preliminary data

SEMD12
NPN/PNP Silicon Digital Transistor Array
Preliminary data
• Switching circuit, inverter, interface circuit,
driver circuit
• Two (galvanic) internal isolated NPN/PNP
Transistors in one package
• Built in bias resistor (R_1=47kΩ, R₂ =47kΩ)
4
5
6
Tape loading orientation
Top View
3 21
45 6
Direction of Unreeling
Marking on SOT666 package
(for example W R)
corresponds to pin 1 of device
Position in tape: pin 1
same of feed hole
side
C1
B2
E2
6
5
4
R₂
R₁
TR2
TR1
R₁
R₂
1
2
3
E1
B1
C2
EHA07176
3
2
1
Type
SEMD12
Marking
W8
Pin Configuration
Package
1=E1 2=B2 3=C2 4=E2 5=B2 6=C1 SOT666
Maximum Ratings
Parameter
Collector-emitter voltage
Collector-base voltage
Emitter-base voltage
Input on Voltage
DC collector current
Total power dissipation, T_S = 75 °C
Junction temperature
Storage temperature
Symbol
V_CEO
V_CBO
V_EBO
V_i(on)
I_C
P_tot
T_j
T_stg
Value
Unit
50
V
50
10
50
70
mA
250
mW
150
°C
-65 ... 150
Thermal Resistance
Junction - soldering point¹⁾
R_thJS
1For _{calculation of RthJA please refer to Application Note Thermal Resistance}
≤ 300
K/W
1
Feb-26-2004