SEMB2 Datasheet, PDF (1/4 Pages) Infineon Technologies AG – PNP Silicon Digital Transistor Array Preliminary data

SEMB2
PNP Silicon Digital Transistor Array
Preliminary data
• Switching circuit, inverter, interface circuit,
driver circuit
4
• Two ( galvanic) internal isolated Transistors
5
3
with good matching in one package
6
2
• Built in bias resistor (R₁=47kΩ, R₂=47kΩ)
1
Type
SEMB2
Marking
WR
C1
B2
E2
6
5
4
R₂
R₁
TR2
TR1
R₁
R₂
1
2
3
E1
B1
C2
EHA07173
Pin Configuration
Package
1=E1 2=B1 3=C2 4=E2 5=B2 6=C1 SOT666
Maximum Ratings
Parameter
Collector-emitter voltage
Collector-base voltage
Emitter-base voltage
Input on Voltage
DC collector current
Total power dissipation, T_S = 75 °C
Junction temperature
Storage temperature
Symbol
V_CEO
V_CBO
V_EBO
V_i(on)
I_C
P_tot
T_j
T_stg
Value
Unit
50
V
50
10
50
70
mA
250
mW
150
°C
-65 ... 150
Thermal Resistance
Junction - soldering point¹⁾
R_thJS
≤ 300
K/W
1For _{calculation of RthJA please refer to Application Note Thermal Resistance}
1
Feb-26-2004