PEF3460E Datasheet, PDF (1/2 Pages) Infineon Technologies AG – Single channel T3/E3 Framer & Line Interface for ATM, Frame Relay and PPP/IP

PRODUCT BRIEF
Single channel T3/E3 Framer & Line
Interface for ATM, Frame Relay
and PPP/IP.
The TE3-FALC^® is a complete solution for a T3/E3
broadband interface. It includes DS3/E3 framing,
analog line interface, two jitter attenuators and the
mapping of ATM or PPP/HDLC. The TE3-FALC^® also
integrates a microcontroller which is running the
device driver and gathering statistics as managed
MIB objects.
On the line side the TE3-FALC^® interfaces to a 75 Ω
co-axial cable via transformers. Highly accurate
analog pulse shaping removes the need to measure
cable length and set the Line Build Out.
On the system side, industry standard UTOPIA and
POS-PHY interface as well as a serial clock/data port
are provided. This allows the TE3-FALC^® to be
connected to a wide array of Layer 2/3 & 4 network
processors.
Applications
s Wireless base stations
s LAN/WAN router
s DSLAMs
s Remote access/concentrator
s Multimedia gateways
Analog Line Interface
s Single channel T3/E3 analog
receive & transmit circuitry
s Identical T3/E3 transformer inter-
face. True software switchable
s Clock & data recovery
s Analog LOS detection
s Single pulse template for all line
length 0 - 450 ft, no need for
setting of Line Build Out
Digital Jitter Attenuator
s Two separate transmit and receive
jitter attenuators
s Meets jitter transfer requirements
s All line rate clocks generated
internally, no requirement for
external 34/45 MHz oscillators
s Clock generation unit accepts
flexible frequency reference clocks,
4 MHz to 52 MHz
T E 3 - FA LC ^{® DS3/E3Framer}
s E3 Framer supporting G.832,
Test and Diagnostic
s JTAG test port
G.751 & TBR24
s OCDS debug port
s DS3 framer supporting M23 and
C-Bit parity modes
s Processing of all DS3 overhead
channels including the FEAC and
Embedded Controller
s Embedded microcontroller with
all code & data memory
MDL link
General Features
s Processing of all E3 overhead
s 3.3 V I/O CMOS technology
channels such as trail trace
s 1.8 V core logic supply
s PLCP sub frame for DS3/E3 G.751 ^{s P-BGA-272 package}
allowing the mapping of ATM cells
27 x 27 mm body size,
s DS3/E3 BERT unit
1.27 mm ball pitch
ATM Cell Processor
s Cell processor as per G.804
s Industrial temperature range
package, -40 °C to +85 °C
s Mapping cells directly into DS3/E3 ^{Key Features}
frames or via PLCP frame
s Integrated T3/E3 analog
PPP Processor
s Bit and byte synchronous HDLC
controller
s Generation and detection of flags,
bit stuffing, CRC-16/32
s Single pulse template for all line
lengths, no LBO requirement
s Jitter attenuation in both Tx and Rx
s Full featured DS3/E3 framer
s ATM and PPP/HDLC mapping
s UTOPIA or POS-PHY interface
System Interfaces
s Integrated µC running S/W driver
s Utopia Level 2 interface 8/16 Bit
s Control via 8/16 Bit Motorola/Intel
s POS-PHY interface 8/16 Bit
µP i/f or inband ATM/PPP
s Serial clock and data interface
messages
s 8/16 Bit Motorola/Intel processor
s High level message based API
interface
T E 3 - F A L C^®
PEF 3460E
www.infineon.com
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