IPD04N03LAG Datasheet, PDF (1/12 Pages) Infineon Technologies AG – OptiMOS®2 Power-Transistor

Type
OptiMOS^®2 Power-Transistor
Package
Marking
• Qualified according to JEDEC¹⁾ for target applications
• N-channel, logic level
• Excellent gate charge x R _DS(on) product (FOM)
• Superior thermal resistance
• 175 °C operating temperature
• Pb-free lead plating; RoHS compliant
IPD04N03LA G IPF04N03LA G
IPS04N03LA G IPU04N03LA G
Product Summary
V _DS
R _DS(on),max (SMD version)
I_D
25 V
3.8 mΩ
50 A
Type
IPD04N03LA
IPF04N03LA
IPS04N03LA
IPU04N03LA
Package
Marking
P-TO252-3-11
04N03LA
P-TO252-3-23
04N03LA
P-TO251-3-11
04N03LA
P-TO251-3-1
04N03LA
Maximum ratings, at T _j=25 °C, unless otherwise specified
Parameter
Symbol Conditions
Continuous drain current
I_D
T _C=25 °C²⁾
Pulsed drain current
I _D,pulse
T _C=100 °C
T _C=25 °C³⁾
Avalanche energy, single pulse
E _AS
I _D=45 A, R _GS=25 Ω
Reverse diode dv /dt
dv /dt
I _D=50 A, V _DS=20 V,
di /dt =200 A/µs,
T _j,max=175 °C
Gate source voltage⁴⁾
V _GS
Power dissipation
P _tot
T _C=25 °C
Operating and storage temperature T _j, T _stg
IEC climatic category; DIN IEC 68-1
Value
50
50
350
600
6
±20
115
-55 ... 175
55/175/56
Unit
A
mJ
kV/µs
V
W
°C
Rev. 1.97
page 1
2006-05-17