IPC302N20NFD Datasheet, PDF (1/3 Pages) Infineon Technologies AG – OptiMOS™3 Power MOS Transistor Chip

IPC302N20NFD
OptiMOS™3 Power MOS Transistor Chip
IPC302N20NFD
Type
IPC302N20NFD
V_(BR)DSS
200 V
R_DS(on)
12 mΩ¹⁾
Die size
6.7 x 4.5mm²
Si-thickness
250 µm
Description
• N-channel enhancement mode
• For dynamic characterization refer to the datasheet of IPP120N20NFD
• AQL 0.65 for visual inspection according to failure catalogue
• Electrostatic Discharge Sensitive Device according to MIL-STD 883C
• Die bond: soldered or glued
• Backside metallization: NiV system
• Frontside metallization: AlSiCu system
• Passivation: nitride and polymide (only on edge structure)
1 Electrical Characteristics on Wafer Level
at Tj = 25 °C, unless otherwise specified.
Parameter
Symbol Value
Unit Conditions
min. typ. max.
Drain-source breakdown voltage V_(BR)DSS
Gate threshold voltage
V_GS(th)
Zero gate voltage drain current I_DSS
Gate-source leakage current
I_GSS
Drain-source on-resistance
R_DS(on)
Reverse diode forward on-voltage V_SD
Avalanche energy, single pulse E_AS
200 -
- V V_GS = 0V
I_D = 1 mA
23
4 V V_DS = V_GS
I_D = 270 µA
- 0.1
1 µA V_GS = 0V
V_DS = 160 V
- 10 100 nA V_GS = 20 V
V_DS = 0 V
- 9.4²⁾ 100 ³⁾ mΩ V_GS= 10 V
I_D= 2.0 A
- 0.65 1.2 V V_GS=0 V
- 45 ⁴⁾
I_F= 1 A
- mJ I_D= 30 A, R_GS=25Ω
1) _{packaged in a PG-TO220-3 (see ref. product)}
2) _{typical bare die RDS(on); VGS=10V}
3) _{limited by wafer test-equipment}
4) _{Wafer tested. For general avalanche capability refer to the datasheet of IPP120N20NFD}
Datasheet
www.infineon.com
1
Rev. 2.0
2016-04-05