IPC26N12NR Datasheet, PDF (1/3 Pages) Infineon Technologies AG – OptiMOSTM3 Power MOS Transistor Chip

IPC26N12NR
OptiMOS^TM3 Power MOS Transistor Chip
Type
IPC26N12NR
V(BR)DSS
120 V
RDS(on)
4.8 mΩ²⁾
Die size
6.0 * 4.36 mm²
Thickness
250 μm
DESCRIPTION
• N-channel enhancement mode
• For additional characteristic and max ratings refer to the datasheet of IPP048N12N3 G ¹⁾
• AQL 0.65 for visual inspection according to failure catalogue
• Electrostatic Discharge Sensitive Device according to MIL-STD 883C
• Die bond: soldered or glued
• Backside metallization: NiV system
• Frontside metallization: AlSi system
• Passivation: nitride (only on edge structure)
Electrical Characteristics on Wafer Level
at Tj = 25 °C, unless otherwise specified.
Parameter
Symbol Value
Unit Conditions
min. typ. max.
Drain-source breakdown voltage V(BR)DSS 120
-
- V V_GS = 0V
I_D = 1 mA
Gate threshold voltage
V GS(th)
2
-
4 V V_DS = V_GS
I_D = 230 μA
Zero gate voltage drain current IDSS
-
0.1
1 μA V_GS = 0V
V_DS = 100 V
Gate-source leakage current
Drain-source on-resistance
IGSS
R_DS(on)
-
1
100 nA V_GS = 20 V
V_DS = 0 V
-
3.2 ⁴⁾ 100 ³⁾ mΩ V_GS= 10 V
I_D= 2.0 A
Reverse diode forward on-voltage VSD
Internal gate resistance
RG
-
1.0 1.2 V V_GS=0 V
I_F= 1 A
-
2
-Ω
Additional gate resistor
Avalanche energy, single pulse
RGadd
EAS
16
Ω
-
45 ⁵⁾
- mJ I_D= 30 A, RGS=25Ω
Infineon Technologies, IMM PSD Rev. 2.1
16.12.2009