IMP16C552 Datasheet, PDF (10/34 Pages) IMP, Inc – Dual Universal Asynchronous Receiver/Transmitter (UART) with 16-BYTE FIFO & Parallel Printer Port

IMP16C552
INTERALL REGISTER DESCRIPTION
The system programmer has access to any of the register as summerized in Table II
Table II Accessible IMP16c552 Registers for each serial channel
Register address
0DLAB=0 0DLAB=0 1DLAB=0
Bit Receiver
Transmitter Interrupt
no Buffer
Holding
Enable
Register
Register
Register
(Read only)
2
Interrupt
Identification
Register
(Read only)
RBR
0 Data Bit 0
THR
Data Bit0
IER
Enable
Receiver
Data register
Interrupt
(ERBF)
IIR
``0”if
Interrupt
Pending
1 Data Bit 1
2 Data Bit 2
3 Data Bit3
4 Data Bit4
Data Bit 1
Data Bit 2
Data Bit3
Data Bit4
Enable
Transmitter
Holding
Register
Empty
Interrupt
(ETBEI)
Enable
Receiver
Line status
interrupt
(ERLS)
Enable
MODEM
Status
interrupt
(EDSSI)
0
Interrupt
ID bit 0
(IIDB0)
Interrupt
ID bit 1
(IIDB1)
Interrupt
ID bit 2
(IIDB2)
0
5 Data Bit5 Data Bit5 0
0
6 Data Bit6 Data Bit6 0
7 Data Bit7 Data Bit7 0
FIFO
Enable(*)
(FE)
FIFO
Enable(*)
(FE)
2
FIFO control
Register
(Write only)
3
Line
Control
Register
FCR
FIFO
Enable
(FEWO)
LCR
Word Length
Select bit 0
(WLSO)
Receiver
FIFO
Reset
(RFR)
Word
length
Select bit 1
(WLS1)
Transmitter
FIFO
Reset
(TFR)
Number of
Stop Bits
(STB)
DMA
Mode
Select
(DMS)
Parity
Enable
(PEN)
Reserved
Reserved
RCVR FIFO
Trigger
Level (LSB)
RCVR FIFO
Trigger
Level (MSB)
Even parity
Select (EPS)
Stick parity
(STP)
Set Break
Control
Divisor Latch
Access bit
(DLAB)
10
408-432-9100/www.impweb.com
© 2002 IMP, Inc.