IMP5115 Datasheet, PDF(1/6 Page) IMP, Inc – 9--Liine SCSII Termiinattor-35MHz Channell Bandwiidtth

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IMP5115 Datasheet, PDF (1/6 Pages) IMP, Inc – 9--Liine SCSII Termiinattor-35MHz Channell Bandwiidtth

I M P 5 1 115

DATA COMMUNICATIONS

9-Line SCSI Terminator

Key Features

â 35MHz Channel Bandwidth

The IMP5115 SCSI terminator is part of IMP's family of high-perfor-

mance, adaptive, non-linear mode SCSI products, which are designed to

deliver true UltraSCSI performance in SCSI applications. The low voltage

BiCMOS architecture employed in its design offers performance superior

to older linear passive and active techniques. IMP's SCSI termination

architecture employs high-speed adaptive elements for each channel,

thereby providing the fastest response possible â typically 35MHz,

which is 100 times faster than the older linear regulator/terminator

approach used by other manufacturers. Products using this older linear

regulator approach have bandwidths which are dominated by the output

capacitor and which are limited to 500KHz (see further discussion in the

Functional Description section). This new architecture also eliminates the

output compensation capacitor required in earlier terminator designs.

Each is approved for use with SCSI-1, -2, -3, UltraSCSI and beyond â

providing the highest performance alternative available today.

x Ultra-Fast response for Fast-20 SCSI applications

x 35MHz channel bandwidth

x 3.3V operation

x Less than 3pF output capacitance

x 375ÂµA Sleep-mode current

x Thermally self limiting

x No external compensation capacitors

x Implements 8-bit or 16-bit (wide) applications

x Compatible with active negation drivers

(60mA/channel)

x Compatible with passive and Active terminations

x Approved for use with SCSI 1, 2, 3 and UltraSCSI

x Hot swap compatible

x Pin-for-pin compatible with DS21S07A/2105

Another key improvement offered by the IMP5115 lies in its ability to

insure reliable, error-free communications even in systems which do not

adhere to recommended SCSI hardware design guidelines, such as the

use of improper cable lengths and impedances. Frequently, this situation

is not controlled by the peripheral or host designer and, when problems

occur, they are the first to be made aware of the problem. The IMP5115

architecture is much more tolerant of marginal system integrations.

Recognizing the needs of portable and configurable peripherals, the

IMP5115 has a TTL compatible sleep/disable mode. Quiescent current

is typically 375ÂµA in this mode, while the output capacitance is also

less than 3pF. The obvious advantage of extended battery life for

portable systems is inherent in the product's sleep-mode feature.

Additionally, the disable function permits factory-floor or production-

line configurability, reducing inventory and product-line

diversity costs. Field configurability can also be accom-

plished without physically removing components which,

often times results in field returns due to mishandling.

Reduced component count is also inherent in the IMP5115

architecture. Traditional termination techniques require

large stabilization and transient protection capacitors of up

to 20ÂµF in value and size. The IMP5115 architecture does

not require these components, allowing all the cost savings

associated with inventory, board space, assembly, reliability,

and component costs.

Block Diagrams

Term Power

Thermal

Limiting

Circuit

Current

Biasing

Circuit

24mA Current

Limiting Circuit

2.85V

DATA OUTPUT

PIN DB (0)

DISABLE PIN

1.4V

1 of 9 Channels

5115_01.eps

Data Communications

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