I642 Datasheet, PDF (1/3 Pages) ILSI America LLC – 3.2 mm x 2.5 mm Ceramic Package SMD VCXO LVCMOS / LVPECL / LVDS

3.2 mm x 2.5 mm Ceramic Package SMD VCXO
LVCMOS / LVPECL / LVDS
I642 Series
Product Features
Small Surface Mount Package
Fast Sample Delivery
Fast Sample Delivery
Pb Free/ RoHS Compliant
Leadfree Processing
Frequency
LVCMOS
LVPECL
LVDS
Output Level
LVCMOS
LVPECL
LVDS
Duty Cycle
LVCMOS
LVPECL
LVDS
Rise / Fall Time
LVCMOS
LVPECL
LVDS
Output Load
LVCMOS
LVPECL
LVDS
Frequency Stability
Supply Voltage (Vcc)
Aging
Current
Linearity
Pullability
Control Voltage
Input Impedance
Phase Jitter (RMS)
At 12kHz to 20 MHz
Operating Temp. Range
Storage Temp. Range
Applications
xDSL
Broadcast Video
Wireless Base Stations
Sonet /SDH
WiMAX/WLAN
Server and Storage
Ethernet/LAN/WAN
Optical modules
Clock and data recovery
FPGA/ASIC
Backplanes
GPON
10.000MHz to 250.000MHz
10.000MHz to 1500.000MHz
10.000MHz to 1500.000MHz
Logic “0” = 10% of Vcc max, Logic “1” = 90% of Vcc min
Logic “0”= Vcc-1.62V max., Logic “1” = 1.02 V min
VOD=(Diff. Output) 350mV Typ.
50% ±5% @ 50% of Vcc
50% ±5% @ 50%*
50% ±5% @ 50%*
2.0 ns max. (10% to 90%)*
0.8 ns max. (20% to 80%)*
0.8 ns max. (20% to 80%)*
15pF
50  to Vcc - 2.0 VDC
RL=100 /CL= 5pF
See Table Below
+3.30 VDC ± 5%, +2.50 VDC ± 5%
±3.0 ppm max per year
HCMOS = 45 mA max
LVPECL = 90 mA max
LVDS = 35 mA max
10% max.
See Table Below
1.65 VDC ± 1.65 VDC @ 3.3V
1.25 VDC ± 1.25 VDC @ 2.5V
50K  min.
0.9 ps typical
See Table Below
-40 C to +85 C
3.20±0.10
Marking
2.50±0.10
1.00±0.15
.60
TYP
123
654
1.30
TYP
1.60
2.30
.70
1.80
.90
.90
.80
Suggested Land Pattern
PIN CONNECTIONS
PIN 1
Voltage Control
PIN 2
Enable/Disable
or N/C
PIN 3
PIN 4
Ground
Output
PIN 5
Comp. Output
or N/C
PIN 6
Voltage Supply
Dimension Units: mm
Package
I642
Part Number Guide
Input
Voltage
Operating
Temperature
3 = 3.3V
6 = 2.5V
1 = 0 C to +70 C
2 = -40 C to +85 C
3 = -20 C to +70 C
Sample Part Number:
I642–31AB9H2–155.520
Stability
(in ppm)
Pullabilty
Output Enable / Disable Complimentary
(Pin 2)
Ouput (Pin 5) **
F = 20
A = 25
B = 50
B =  50
C = 100
3 = LVCMOS
8 = LVDS
9 = LVPECL
H = Enable
O = N/C
1 = N.C.
2 = Output
Frequency
-155.520 MHz
NOTE: A 0.01 µF bypass capacitor is recommended between V_DD (pin 6) and GND (pin 3) to minimize power supply noise. * Measured as percent of
waveform. ** Available on LVDS and LVPECL ouput only.
ILSI America Phone [phone] ● Fax [phone] ●email: [e-mail] ●
www.ilsiamerica.com
Specifications subject to change without notice
Rev: 03/10/15_A
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