IW4015B Datasheet, PDF (4/6 Pages) Integral Corp. – Dual 4-Stage Static Shift Register High-Voltage Silicon-Gate CMOS

IW4015B
AC ELECTRICAL CHARACTERISTICS (C_L=50pF, R_L=200kΩ, Input t_r=t_f=20 ns)
V_CC
Guaranteed Limit
Symbol
Parameter
V ≥-55°C 25°C ≤125°C
t_max Maximum Clock Frequency (Figure 1)
5.0
3
10
6
15 8.5
3
1.5
6
3
8.5
4.25
t_PHL, t_PLH Maximum Propagation Delay, Clock to Q
(Figure 1)
5.0 320
320
640
10 160
160
320
15 120
120
240
t_PHL Maximum Propagation Delay, Reset to Q
(Figure 2)
5.0 400
400
800
10 200
200
400
15 160
160
320
t_THL, t_TLH Maximum Output Transition Time, Any Output 5.0 200
200
400
(Figure 1)
10 100
100
200
15
80
80
160
C_IN Maximum Input Capacitance
-
7.5
Unit
MHz
ns
ns
ns
pF
TIMING REQUIREMENTS(C_L=50pF, R_L=200 kΩ, Input t_r=t_f=20 ns)
Symbol
Parameter
t_w
Minimum Pulse Width, Clock (Figure 1)
t_w
Minimum Pulse Width, Reset (Figure 2)
t_su
Minimum Setup Time, Data to Clock
(Figure 3)
t_h
Minimum Hold Time, Clock to Data
(Figure 3)
t_r, t_f Maximum Input Rise and Fall Time (Figure 1)
V_CC
Guaranteed Limit
V ≥-55°C 25°C ≤125°C Unit
5.0 180
180
360
ns
10
80
80
160
15
50
50
100
5.0 200
200
400
ns
10
80
80
160
15
60
60
120
5.0 70
10
40
15
30
70
140
ns
40
80
30
60
5.0
0
0
0
ns
10
0
0
0
15
0
0
0
5.0 15
15
30
μs
10
6
6
12
15
2
2
4
Rev. 00