IN74HC10A Datasheet, PDF (4/5 Pages) Integral Corp. – Triple 3-Input NAND Gate High-Performance Silicon-Gate CMOS

IN74HC10A
AC ELECTRICAL CHARACTERISTICS (C_L=50pF,Input t_r=t_f=6.0 ns)
Symbol
Parameter
t_PLH, t_PHL Maximum Propagation Delay, Input A,B or C to
Output Y (Figures 1 and 2)
t_TLH, t_THL Maximum Output Transition Time, Any Output
(Figures 1 and 2)
C_IN Maximum Input Capacitance
V_CC
Guaranteed Limit
V 25 °C ≤85°C ≤125°C Unit
to
-55°C
2.0 95
4.5 19
6.0 16
120
145
ns
24
29
20
25
2.0 75
4.5 15
6.0 13
95
110
ns
19
22
16
19
-
10
10
10
pF
Power Dissipation Capacitance (Per Gate)
C_PD Used to determine the no-load dynamic power
consumption:
P_D=C_PDV_CC2f+I_CCV_CC
Typical @25°C,V_CC=5.0 V
25
pF
Figure 1. Switching Waveforms
Figure 2. Test Circuit
EXPANDED LOGIC DIAGRAM
(1/3 of the Device)
Rev. 00