IN16C554A Datasheet, PDF (17/31 Pages) IK Semicon Co., Ltd – Independent receiver clock input

IN16C554A
Quadruple UART
February 2009 REV 1.01
7.3 FIFO Control Register (FCR)
FCR is used for enabling the FIFOs, clearing the FIFOs, setting transmit/receive FIFO
trigger level, and selecting the DMA modes. Table 11 shows FCR bit settings.
Table 9: FIFO Control Register Description
Bit Symbol Description
7:6 FCR[7:6] RX FIFO Trigger Level Select
00 : 1 characters (default)
01 : 4 characters
10 : 8 characters
11 : 14 characters
5:4 FCR[5:4] FCR[5:4] are reserved
3
FCR[3]
DMA Mode Select
0 : Set DMA mode 0 (default)
1 : Set DMA mode 1
2
FCR[2]
TX FIFO Reset
0 : No TX FIFO reset (default)
1 : Reset TX FIFO pointers and TX FIFO level counter logic.
This bit will return to ‘0’ after resetting FIFO.
1
FCR[1]
RX FIFO Reset
0 : No RX FIFO reset (default)
1 : Reset RX FIFO pointers and RX FIFO level counter logic.
This bit will return to ‘0’ after resetting FIFO.
0
FCR[0]
FIFO enable
0 : Disable the TX and RX FIFO (default).
1 : Enable the TX and RX FIFO
7.4 Line Control Register (LCR)
LCR controls the asynchronous data communication format. The word length, the number
of stop bits, and the parity type are selected by writing the appropriate bits to the LCR.
Table 12 shows LCR bit settings.
Table 10: Line Control Register Description
Bit Symbol
7
LCR[7]
6
LCR[6]
5
LCR[5]
Description
Divisor Latch Enable.
0 : Disable the divisor latch (default).
1 : Enable the divisor latch.
Break Enable.
0 : No TX break condition output (default).
1 : Forces TXD output to ‘0’, for alerting the communication
terminal to a line break condition.
Set Stick Parity.
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