IN74LV574 Datasheet, PDF (1/8 Pages) Integral Corp. – Octal D-type flip-flop; positive edge-trigger (3-State)

TECHNICAL DATA
IN74LV574
Octal D-type flip-flop;
positive edge-trigger (3-State)
The 74LV574 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT574.
The 74LV574 is an octal D-type flip–flop featuring separate D-type
inputs for each flip-flop and non-inverting 3-state outputs for oriented
applications. A clock (CP) and an output enable (OE) input are common to
all flip-flops. The eight flip-flops will store the state of their individual D-
inputs that meet the set-up and hold times requirements on the LOW-to-
HIGH CP transition. When OE is LOW, the contents of the eight flip-flops
are available at the outputs. When OE is HIGH, the outputs go to the high
impedance OFF-state. Operation of the OE input does not affect the state of
the flip-flops.
• Output voltage levels are compatible with input levels of CMOS,
NMOS and TTL IC_S
• Supply voltage range: 1.0 to 5.5 V
• Low input current: 1.0 µА; 0.1 µА at Т = 25 °С
• High Noise Immunity Characteristic of CMOS Devices
N SUFFIX
PLASTIC DIP
20
1
20
1
DW SUFFIX
SO
ORDERING INFORMATION
IN74LV574N
Plastic DIP
IN74LV574DW SOIC
T_A = -40° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 20=V_CC
PIN 10 = GND
FUNCTION TABLE
Inputs
Output Clock
D
Enable
L
H
L
L
L L,H,
X
H
X
X
H= high level
L = low level
X = don’t care
Z = high impedance
Output
Q
H
L
no
change
Z
1