IDT82V3390 Datasheet, PDF (9/182 Pages) Integrated Device Technology – SYNCHRONOUS ETHERNET IDT WAN PLL™

SYNCHRONOUS ETHERNET
WAN PLL
Datasheet
IDT82V3390
FEATURES
HIGHLIGHTS
• Single PLL chip:
• Features 0.5 mHz to 560 Hz bandwidth
• Provides node clock for ITU-T G.8261/G.8262 Synchronous
Ethernet (SyncE)
• Exceeds GR-253-CORE and ITU-T G.813 jitter generation
requirements
• Provides node clocks for Cellular and WLL base-station (GSM
and 3G networks)
• Provides clocks for DSL access concentrators (DSLAM), espe-
cially for Japan TCM-ISDN network timing based ADSL equip-
ments
• Provides clocks for 1 Gigabit and 10 Gigabit Ethernet applica-
tions
MAIN FEATURES
• Provides an integrated single-chip solution for Synchronous Equip-
ment Timing Source, including Stratum 3, Stratum 4E, Stratum 4,
SMC, EEC-Option 1 and EEC-Option 2 Clocks
• Provides 156.25 MHz clock for 10 Gig Ethernet Application, with
less than 0.7 ps of RMS Phase Jitter (12 kHz - 20 MHz)
• Employs PLL architecture to feature excellent jitter performance
and minimize the number of the external components
• Integrates T0 DPLL and T4 DPLL; T4 DPLL locks independently or
locks to T0 DPLL
• Supports Forced or Automatic operating mode switch controlled by
an internal state machine. It supports Free- Run, Locked and Hold-
over modes
• Supports programmable DPLL bandwidth (0.5 mHz to 560 Hz in 19
steps) and damping factor (1.2 to 20 in 5 steps)
• Supports 1.1X10^-5 ppm absolute holdover accuracy and 4.4X10^-8
ppm instantaneous holdover accuracy
• Supports hitless reference switching to minimize phase transients
on T0 DPLL output to be no more than 0.61 ns
• Supports phase absorption when phase-time changes on T0
selected input clock are greater than a programmable limit over an
interval of less than 0.1 seconds
• Supports programmable input-to-output phase offset adjustment
• Limits the phase and frequency offset of the outputs
• Provides OUT1~OUT7 output clock frequencies covering from 2
kHz to 625MHz
• Includes 125 MHz and 156.25 MHz for CMOS outputs
• Includes 125 MHz, 156.25 MHz, 312.5 MHz and 625 MHz for dif-
ferential outputs
• Provides OUT8 for composite clocks and OUT9 for 1.544 MHz/
2.048 MHz (BITS/SSU)
• Provides IN1 and IN2 for composite clocks
• Provides IN3~IN14 input clock frequencies covering from 2 kHz to
625 MHz
• Includes 125 MHz and 156.25 MHz for CMOS inputs
• Includes 156.25 MHz, 312.5 MHz and 625 MHz for differential
inputs
• Supports manual and automatic selected input clock switch
• Supports automatic hitless selected input clock switch on clock fail-
ure
• Supports three types of input clock sources: recovered clock from
STM-N or OC-n, PDH network synchronization timing and external
synchronization reference timing
• Provides a 2 kHz, 4 kHz or 8 kHz frame sync input signal, and a 2
kHz and an 8 kHz frame sync output signals
• Provides output clocks for BITS, GPS, 3G, GSM, etc.
• Supports AMI, PECL/LVDS and CMOS input/output technologies
• Supports master clock calibration
• Supports Master/Slave application (two chips used together) to
enable system protection against single chip failure
• Supports Telcordia GR-1244-CORE, Telcordia GR-253-CORE,
ITU-T G.812, ITU-T G.8262. ITU-T G.813 and ITU-T G.783 Recom-
mendations
OTHER FEATURES
• Multiple microprocessor interface modes: EPROM, Multiplexed,
Intel, Motorola, I2C and Serial
• IEEE 1149.1 JTAG Boundary Scan
• Single 3.3 V operation with 5 V tolerant CMOS I/Os
• 100-pin TQFP package, green package options available
APPLICATIONS
• 1 Gigabit Ethernet and 10 Gigabit Ethernet
• BITS / SSU
• SMC / SEC (SONET / SDH)
• DWDM cross-connect and transmission equipment
• Synchronous Ethernet equipment
• Central Office Timing Source and Distribution
• Core and access IP switches / routers
• Gigabit and terabit IP switches / routers
• IP and ATM core switches and access equipment
• Cellular and WLL base-station node clocks
• Broadband and multi-service access equipment
• Any other telecom equipments that need synchronous equipment
system timing
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
9
 2011 Integrated Device Technology, Inc.
July 14, 2011
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