IDT71P73204 Datasheet, PDF (9/25 Pages) Integrated Device Technology – 18Mb Pipelined DDR™II SRAM Burst of 4

IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 4
Commercial Temperature Range
Write Descriptions^(1,2)
Signal
BW0 BW1 BW2 BW3 NW0 NW1
Write Byte 0
L
X
X
X
X
X
Write Byte 1
X
L
X
X
X
X
Write Byte 2
X
X
L
X
X
X
Write Byte 3
X
X
X
L
X
X
Write Nibble 0
X
X
X
X
L
X
Write Nibble 1
X
X
X
X
X
L
NOTES:
6431 tbl 09
1) All byte write (BWx) and nibble write (NWx) signals are sampled on
the rising edge of K and again on K. The data that is present on the data
bus in the designated byte/nibble will be latched into the input if the
corresponding BWx or NWx is held low. The rising edge of K will sample
the first and third bytes/nibbles of the four word burst and the rising edge
of K will sample the second and fourth bytes/nibbles of the four word
burst.
2) The availability of the BWx or NWx on designated devices is de-
scribed in the pin description table.
3) The DDRII Burst of four SRAM has data forwarding. A read request
that is initiated on the cycle following a write request to the same address
will produce the newly written data in response to the read request.
Linear Burst Sequence Table ^(1,2)
SA [1:0]
a
b
c
d
00
00
01
10
01
01
10
11
10
10
11
00
11
11
00
01
NOTES:
1. SA [1:0] is the address presented on pins SA1 and SA0 giving the burst sequence a,b,c,d.
2. SA0 and SA1 are only available on the x18 and x36-bit devices.
11
00
01
10
6431 tbl 22
6.942