IDT5T93GL04 Datasheet, PDF (9/17 Pages) Integrated Device Technology – 2.5V LVDS, 1:4 GLITCHLESS CLOCK BUFFER TERABUFFERII

IDT5T93GL04
2.5V LVDS 1:4 GLITCHLESS CLOCK BUFFER TERABUFFER™ II
Differential AC Timing Waveforms
Output Propagation and Skew Waveforms
1/fo
A[1:2] - A[1:2]
+ VDIF
VDIF = 0
- VDIF
Qn - Qn
Qm - Qm
tPLH
tSK(O)
tPHL
tSK(O)
+ VDIF
VDIF = 0
- VDIF
+ VDIF
VDIF = 0
- VDIF
NOTE 1: Pulse skew is calculated using the following expression:
tsk(p) = |tp_HL – tp_LH|
Note that the tp_HL and tp_LH shown above ae not valid measurements for this calculation because they are not taken from the same pulse.
NOTE 2: AC propagation measurements should not be taken within the first 100 cycles of startup.
Differential Gate Disabled/Endable Showing Runt Pulse Generation
A[1:2] - A[1:2]
+ VDIF
VDIF = 0
- VDIF
VIH
GL
VTHI
VIL
tPLH
G
VIH
VTHI
VIL
Qn - Qn
tPGD
tPGE
+ VDIF
VDIF = 0
- VDIF
NOTE 1: As shown, it is possible to generate runt pulses on gate disable and enable of the outputs. It is the user’s responsibility to time
the G signal to avoid this problem.
IDT™ LVDS GLITCHLESS CLOCK BUFFER TERABUFFER™ II
9
IDT5T93GL04 REV. A JULY 10, 2007