IDT5T9306_08 Datasheet, PDF (9/14 Pages) Integrated Device Technology – 2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II

IDT5T9306
2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II
A[1:2] - A[1:2]
GL
G
Qn - Qn
tPLH
tPGD
tPGE
+ VDIF
VDIF = 0
- VDIF
VIH
VTHI
VIL
VIH
VTHI
VIL
+ VDIF
VDIF = 0
- VDIF
Differential Gate Disable/Enable Showing Runt Pulse Generation
NOTE:
1. As shown, it is possible to generate runt pulses on gate disable and enable of the outputs. It is the user's responsibility to time the G signal to avoid this problem.
A1 - A1
+VDIF
VDIF=0
-VDIF
A2 - A2
G
+VDIF
VDIF=0
-VDIF
VIH
VTHI
VIL
VIH
PD
VTHI
VIL
Qn - Qn
+VDIF
VDIF=0
-VDIF
Power Down Timing
NOTES:
1. It is recommended that outputs be disabled before entering power-down mode. It is also recommended that the outputs remain disabled until the device completes power-up after
asserting PD.
2. The POWER DOWN TIMING diagram assumes that GL is HIGH.
3. It should be noted that during power-down mode, the outputs are both pulled to VDD. In the POWER DOWN TIMING diagram this is shown when Qn-Qn goes to VDIF = 0.
IDT^™ / ICS^™ LVDS CLOCK BUFFER TERABUFFER™ II
9
IDT5T9306 REV. B APRIL 15, 2008