IDT1337AG Datasheet, PDF (9/26 Pages) Integrated Device Technology – Oscillator Stop Flag

IDT1337AG
REAL-TIME CLOCK WITH I²C SERIAL INTERFACE
RTC
Bit 2: Interrupt Control (INTCN). This bit controls the relationship between the two alarms and the interrupt output
pins. When the INTCN bit is set to logic 1, a match between the timekeeping registers and the alarm 1 registers
activate the INTA pin (provided that the alarm is enabled) and a match between the timekeeping registers and the
alarm 2 registers activates the SQW/INTB pin (provided that the alarm is enabled). When the INTCN bit is set to
logic 0, a square wave is output on the SQW/INTB pin.This bit is set to logic 0 when power is first applied.
Bit 1: Alarm 2 Interrupt Enable (A2IE). When set to a logic 1, this bit permits the Alarm 2 Flag (A2F) bit in the
status register to assert INTA (when INTCN = 0) or to assert SQW/INTB (when INTCN = 1). When the A2IE bit is
set to logic 0, the A2F bit does not initiate an interrupt signal. The A2IE bit is disabled (logic 0) when power is first
applied.
Bit 0: Alarm 1 Interrupt Enable (A1IE). When set to logic 1, this bit permits the Alarm 1 Flag (A1F) bit in the status
register to assert INTA. When the A1IE bit is set to logic 0, the A1F bit does not initiate the INTA signal. The A1IE
bit is disabled (logic 0) when power is first applied.
Table 4. Alarm/Interrupt Table
Bit 2
INTCN
0
0
0
0
1
1
1
1
Bit 1
A2IE
0
0
1
1
0
0
1
1
Bit 0
A1IE
0
1
0
1
0
1
0
1
Alarm 1
None
INTA
None
INTA
None
INTA
None
INTA
Alarm 2
None
None
INTA
INTA
None
None
INTB
INTB
INTA
Hi
Alarm 1
Alarm 2
Alarm 1 or Alarm 2
Hi
Alarm 1
Hi
Alarm 1
INTB/SQW
SQW
SQW
SQW
SQW
Hi
Hi
Alarm 2
Alarm 2
IDT® REAL-TIME CLOCK WITH I²C SERIAL INTERFACE
9
IDT1337AG REV C 011514