ICS8538-31 Datasheet, PDF (9/14 Pages) Integrated Device Technology – LOW SKEW, 1-TO-8, CRYSTAL OSCILLATOR/LVCMOS-TO-3.3V LVPECL FANOUT BUFFER

ICS8538-31
LOW SKEW, 1-TO-8, CRYSTAL OSCILLATOR/LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS8538-31.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8538-31 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V_CC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core)_MAX = V_{CC_MAX} * I_{EE_MAX} = 3.465V * 110mA = 381.15mW
• Power (outputs)_MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 8 * 30mW = 240mW
Total Power__MAX (3.3V, with all outputs switching) = 381.15mW + 240mW = 621.15mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θ_JA * Pd_total + T_A
Tj = Junction Temperature
θ_JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T_A = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ_JA must be used. Assuming no air flow
and a multi-layer board, the appropriate value is 49.8°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.621W * 49.8°C/W = 100.9°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (single layer or multi-layer).
Table 7. Thermal Resistance θ_JA for 28 Lead TSSOP, Forced Convection
θ_JA by Velocity
Linear Feet per Minute
0
Single-Layer PCB, JEDEC Standard Test Boards
82.9°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
49.8°C/W
200
68.7°C/W
43.9°C/W
NOTE: Most modern PCB design use multi-layered boards. The data in the second row pertains to most designs.
500
60.5°C/W
41.2°C/W
IDT™ / ICS™ LVPECL FANOUT BUFFER
9
ICS8538BG-31 REV. B FEBRUARY 5, 2008