ICS844021-01 Datasheet, PDF (9/13 Pages) Integrated Device Technology – FEMTOCLOCKS™ CRYSTAL-TO-LVDS CLOCK GENERATOR

ICS844021-01
FEMTOCLOCKS™ CRYSTAL-TO-LVDS CLOCK GENERATOR
POWER CONSIDERATIONS
PRELIMINARY
This section provides information on power dissipation and junction temperature for the ICS844021-01
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS844021-01 is the sum of the core power plus the analog plus the power dissipated in the
load(s).
The following is the power dissipation for V = 3.3V + 5% = 3.465V, which gives worst case results.
DD
• Power (core) = V * (I + I ) = 3.465V * (55mA + 8mA) = 218.3mW
MAX
DD_MAX
DD_MAX
DDA_MAX
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS^TM devices is 125°C.
The equation for Tj is as follows: Tj = θ * Pd_total + T
JA
A
Tj = Junction Temperature
θ_JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T = Ambient Temperature
A
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ_JA must be used. Assuming no air
flow and a multi-layer board, the appropriate value is 129.5°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.218W * 129.5°C/W = 98.2°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and
the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θ FOR 8-LEAD TSSOP, FORCED CONVECTION
JA
θ by Velocity (Meters per Second)
JA
Multi-Layer PCB, JEDEC Standard Test Boards
0
129.5°C/W
1
125.5°C/W
2.5
123.5°C/W
IDT^™ / ICS^™ LVDS CLOCK GENERATOR
9
ICS844021BG-01 REV. C SEPTEMBER 27, 2007