8T49N242_16 Datasheet, PDF (9/63 Pages) Integrated Device Technology – FemtoClock NG Universal Frequency Translator

8T49N242 Datasheet
Output Phase Control on Switchover
There are two options on how the output phase can be controlled
when the 8T49N242 enters or leaves the holdover state, or the PLL
switches between input references. Phase-slope limiting or fully
hitless switching (sometimes called phase build-out) may be
selected. The SWMODE bit selects which behavior is to be followed.
If fully hitless switching is selected, then the output phase will remain
unchanged under any of these conditions. Note that fully hitless
switching is not supported when external loopback is being used.
Fully hitless switching should not be used unless all input references
are in the same clock domain. Note that use of this mode may
prevent an output frequency and phase from being able to trace its
alignment back to a primary reference source.
If phase-slope limiting is selected, then the output phase will adjust
from its previous value until it is tracking the new condition at a rate
dictated by the SLEW[1:0] bits. Phase-slope limiting should be used
if all input references are not in the same clock domain or users wish
to retain traceability to a primary reference source.
Output Drivers
The Q0 to Q3 clock outputs are provided with register-controlled
output drivers. By selecting the output drive type in the appropriate
register, any of these outputs can support LVCMOS, LVPECL, HCSL
or LVDS logic levels.
The operating voltage ranges of each output is determined by its
independent output power pin (V_CCO) and thus each can have
different output voltage levels. Output voltage levels of 2.5V or 3.3V
are supported for differential operation and LVCMOS operation. In
addition, LVCMOS output operation supports 1.8V V_CCO.
Each output may be enabled or disabled by register bits and/or GPIO
pins.
LVCMOS Operation
When a given output is configured to provide LVCMOS levels, then
both the Q and nQ outputs will toggle at the selected output
frequency. All the previously described configuration and control
apply equally to both outputs. Frequency, voltage levels and enable /
disable status apply to both the Q and nQ pins. When configured as
LVCMOS, the Q & nQ outputs can be selected to be phase-aligned
with each other or inverted relative to one another. Selection of
phase-alignment may have negative effects on the phase noise
performance of any part of the device due to increased simultaneous
switching noise within the device.
Power-Saving Modes
To allow the device to consume the least power possible for a given
application, the following functions can be disabled via register
programming:
• Any unused output, including all output divider logic, can be
individually powered-off.
• Any unused input, including the clock monitoring logic can be
individually powered-off.
• The digital PLL can be powered-off when running in synthesizer
mode.
• Clock gating on logic that is not being used.
Status / Control Signals and Interrupts
The status and control signals for the device, may be operated at
1.8V, 2.5V or 3.3V as determined by the voltage applied to the V_CCCS
pins. All signals will share the same voltage levels.
Signals involved include: nWP, nINT, nRST, GPIO[3:0], S_A0, S_A1,
SCLK and SDATA. The voltage used here is independent of the
voltage chosen for the digital and analog core voltages and the
output voltages selected for the clock outputs.
General-Purpose I/Os & Interrupts
The 8T49N242 provides four General Purpose Input / Output (GPIO)
pins for miscellaneous status & control functions. Each GPIO may be
configured as either an input or an output. Each GPIO may be directly
controlled from register bits or be used as a predefined function as
shown in Table 4. Note that the default state prior to configuration
being loaded from internal OTP will be to set each GPIO to input
direction to function as an Output Enable.
Table 4. GPIO Configuration¹
Configured as Input
Configured as Output
GPIO
Pin
Fixed
Function
(default)
General
Purpose
Fixed
Function
General
Purpose
3
-
GPI[3]
LOL
GPO[3]
2
CSEL
GPI[2]
LOS[0]
GPO[2]
1
OSEL[1]
GPI[1]
LOS[1]
GPO[1]
0
OSEL[0]
GPI[0]
HOLD
GPO[0]
NOTE 1: GPI[x]: General Purpose Input. Logic state on GPIO[x] pin
is directly reflected in GPI[x] register.
LOL: Loss-of-Lock Status Flag for Digital PLL. Logic-high indicates
digital PLL not locked.
GPO[x]: General Purpose Output. Logic state is determined by value
written in register GPO[x].
OSEL[n]: Output Enable Control Signals for Outputs Qx, nQx. Refer
to Section, “Output Enable Operation”.
LOS[x]: Loss-of-Signal Status Flag for Input Reference x. Logic-high
indicates input reference failure.
CSEL: Manual Clock Select Input for PLL. Logic-high selects differ-
ential clock input 1 (CLK1).
HOLD: Holdover Status Flag for Digital PLL. Logic-high indicates dig-
ital PLL in holdover status.
Refer to Section, “Register Descriptions” for additional details.
If used in the Fixed Function mode of operation, the GPIO bits will
reflect the real-time status of their respective status bits as shown in
Table 4.
The LOL alarm will support two modes of operation:
• De-asserts once PLL is locked, or
• De-asserts after PLL is locked and all internal synchronization
operations that may destabilize output clocks are completed.
©2016 Integrated Device Technology, Inc.
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Revision 6, November 1, 2016