8P73S674 Datasheet, PDF (9/15 Pages) Integrated Device Technology – Clock signal division and distribution

8P73S674 DATA SHEET
Power Considerations
This section provides information on power dissipation and junction temperature for the 8P73S674. 
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 8P73S674 is the sum of the core power plus the power dissipated due to loading. 
The following is the power dissipation for V_CC = 1.8V + 0.15V = 1.95V, which gives worst case results.
The following calculation is for 85°C. The maximum current at 85°C is 68.3mA.
NOTE: Please refer to Section 3 for details on calculating power dissipated due to loading.
• Power (core)_MAX = V_{CC_MAX} * I_{CC_MAX} = 1.95V * 68.3mA = 133.2mW
• Power (outputs)_MAX = 31.5mW/Loaded Output pair
If all outputs are loaded, the total power is 4 * 31.5mW = 126mW
• Power Dissipation for internal termination R_T
Power (R_T)_MAX = 2 * [(I_{IN_MAX})² * 50] = 2 * (25mA)² * 50 = 62.5mW
Total Power__MAX = Power (core)_MAX + Power (outputs)_MAX + Power (R_T)_MAX = 133.2+ 126mW + 62.5mW = 321.7mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and it directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = _JA * Pd_total + T_A
Tj = Junction Temperature
_JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T_A = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance _JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 62.2°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.322W * 70.7°C/W = 108°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance _JA for 20-Lead VFQFN, Forced Convection
Meters per Second
_JA by Velocity
0
Multi-Layer PCB, JEDEC Standard Test Boards
70.7°C/W
1
67.0°C/W
2
65.3°C/W
REVISION 1 12/17/14
9
1.8V LVPECL CLOCK DIVIDER