5P49V6913 Datasheet, PDF (9/36 Pages) Integrated Device Technology – Programmable Clock Generator

I²C Mode Operation
The device acts as a slave device on the I²C bus using one of
the two I²C addresses (0xD0 or 0xD4) to allow multiple
devices to be used in the system. The interface accepts
byte-oriented block write and block read operations. Two
address bytes specify the register address of the byte position
of the first register to write or read. Data bytes (registers) are
accessed in sequential order from the lowest to the highest
byte (most significant bit first). Read and write block transfers
can be stopped after any complete byte transfer. During a
write operation, data will not be moved into the registers until
the STOP bit is received, at which point, all data received in
the block write will be written simultaneously.
For full electrical I²C compliance, it is recommended to use
external pull-up resistors for SDATA and SCLK. The internal
pull-down resistors have a size of 100k typical.
5P49V6913 DATASHEET
Current Read
S
Dev Addr + R
A
Data 0
A
Data 1
A
A
Data n
Abar P
Sequential Read
S
Dev Addr + W
A
Reg start Addr
A
Sr
Dev Addr + R
A
Data 0
A
Data 1
A
A
Sequential Write
S
Dev Addr + W
A
Reg start Addr
A
Data 0
A
Data 1
A
A
Data n
A
P
Data n
Abar P
from master to slave
from slave to master
S = start
Sr = repeated start
A = acknowledge
Abar= none acknowledge
P = stop
I²C Slave Read and Write Cycle Sequencing
NOVEMBER 11, 2016
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PROGRAMMABLE CLOCK GENERATOR