IDT82P2282 Datasheet, PDF (86/383 Pages) Integrated Device Technology – Dual T1/E1/J1 Long Haul / Short Haul Transceiver

IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
3.20.2.3 Interrupt Summary
In both of the two HDLC modes, when the data in the FIFO is below
the lower threshold set by the LL[1:0] bits, it will be indicated by the RDY
bit. When there is a transition (from ‘0’ to ‘1’) on the RDY bit, the RDYI
bit will be set. In this case, if enabled by the RDYE bit, an interrupt will
be reported by the INT pin.
In both of the two HDLC modes, when the FIFO is empty and the
last transmitted byte is not the end of the current HDLC/SS7 packet, the
UDRUNI bit will be set. In this case, if enabled by the UDRUNE bit, an
interrupt will be reported by the INT pin.
3.20.2.4 Reset
The HDLC Transmitter will be reset when there is a transition from
‘0’ to ‘1’ on the TRST bit. The reset will clear the FIFO.
Table 52: Related Bit / Register In Chapter 3.20.2.2 ~ Chapter 3.20.2.4
Bit
THDLCM
EOM
ABORT
XREP
AUTOFISU
TRST
DAT[7:0]
FUL
EMP
RDY
TDLEN3
TDLEN2
TDLEN1
HL[1:0]
FL[1:0]
LL[1:0]
RDYI
UDRUNI
RDYE
UDRUNE
Register
THDLC1 Control / THDLC2 Control / THDLC3 Control
THDLC1 Data / THDLC2 Data / THDLC3 Data
TFIFO1 Status / TFIFO2 Status / TFIFO3 Status
THDLC Enable Control
TFIFO1 Threshold / TFIFO2 Threshold / TFIFO3 Threshold
THDLC1 Interrupt Indication / THDLC2 Interrupt Indication /
THDLC3 Interrupt Indication
THDLC1 Interrupt Control / THDLC2 Interrupt Control / THDLC3
Interrupt Control
Address (Hex)
0A7, 1A7 / 0A8, 1A8 / 0A9, 1A9
0AD, 1AD / 0AE, 1AE / 0AF, 1AF
0B0 / 0B1, 1B1 / 0B2, 1B2
084, 184
0AA, 1AA / 0AB, 1AB / 0AC, 1AC
0B6, 1B6 / 0B7, 1B7 / 0B8, 1B8
0B3, 1B3 / 0B4, 1B4 / 0B5, 1B5
75
October 7, 2003