ICS98UAE877A Datasheet, PDF (8/18 Pages) Integrated Device Technology – 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER

ICS98UAE877A
1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER
COMMERCIAL TEMPERATURE GRADE
Timing Requirements Over Recommended Operating Free-Air Temperature
Range
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = 0°C to +70°C, Industrial: TA = -40°C to +85°C; Supply Voltage AVDD/VDDQ = 1.5V ± 0.075V.
Symbol
freqOP
freqAPP
Parameter¹
Max Clock Frequency²
Application Frequency Range³
Conditions
1.5V ± 0.075V @ 25°C
1.5V ± 0.075V @ 25°C
Min.
95
160
Max.
410
410
Units
MHz
MHz
dTIN
TSTAB
Input Clock Duty Cycle
CLK Stabilization⁴
40
60
%
9
μs
1 The PLL must be able to handle spread spectrum induced skew.
2 Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is
not required to meet the other timing parameters. (Used for low speed system debug.)
3 Application clock frequency indicates a range over which the PLL must meet all timing parameters.
4 Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback
signal to its reference signal, within the value specificied by the Static Phase Offset (t∅), after power-up.
During normal operation, the stabilization time is also the time required for the integrated PLL circuit to ob-
tain phase lock of its feedback signal to its reference signal when CLK and CLK go to a logic low state,
enter the power-down mode and later return to active operation. CLK and CLK may be left floating after
they have been driven low for one complete clock cycle.
1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER
8
ICS98UAE877A
7181/2