ICS853111B Datasheet, PDF (8/19 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER

ICS853111B
LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVCMOS LEVELS
Figure 2A shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF ~ V /2 is
CC
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V = 3.3V, V_REF should be 1.25V
CC
and R2/R1 = 0.609.
VCC
Single Ended Clock Input
R1
1K
PCLKx
V_REF
C1
0.1u
nPCLKx
R2
1K
FIGURE 2A. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVPECL LEVELS
Figure 2B shows an example of the differential input that can
be wired to accept single ended LVPECL levels. The reference
voltage level V generated from the device is connected to the
BB
negative input. The C1 capacitor should be located as close as
possible to the input pin.
VDD(or VCC)
CLK_IN
C1
0.1uF
+
VBB
-
FIGURE 2B. SINGLE ENDED LVPECL SIGNAL DRIVING DIFFERENTIAL INPUT
IDT^™ / ICS^™ 1-TO-10, LVPECL/ECL FANOUT BUFFER
8
ICS853111BY REV. B SEPTEMBER 5, 2007