ICS853052 Datasheet, PDF (8/14 Pages) Integrated Circuit Systems – DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V, 3.3V, 5V LVPECL MULTIPLEXER

ICS853052
DUAL LVCMOS/LVTTL-TO-DIFFERENTIAL 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
PRELIMINARY
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
transmission lines. Matched impedance techniques should be
used to maximize operating frequency and minimize signal dis-
tortion. Figures 2A and 2B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts
may exist and it would be recommended that the board design-
ers simulate to guarantee compatibility across all printed circuit
and clock component process variations.
Z_o = 50Ω
FOUT
FIN
Z_o = 50Ω
50Ω
RTT =
1
((V_OH + V_OL) / (V_CC – 2)) – 2
Z_o
50Ω
V_CC - 2V
RTT
FOUT
3.3V
125Ω
125Ω
Z_o = 50Ω
FIN
Z_o = 50Ω
84Ω
84Ω
FIGURE 2A. LVPECL OUTPUT TERMINATION
FIGURE 2B. LVPECL OUTPUT TERMINATION
TERMINATION FOR 5V LVPECL OUTPUT
This section shows examples of 5V LVPECL output termination.
Figure 3A shows standard termination for 5V LVPECL. The
termination requires matched load of 50Ω resistors pull down to
V - 2V = 3V at the receiver. Figure 3B shows Thevenin
CC
equivalence of Figure 3A. In actual application where the 3V DC
power supply is not available, this approached is normally used.
5V
PEC L
Zo = 50 Ohm
Zo = 50 Ohm
R1
R2
50
50
3V
5V
+
-
PECL
FIGURE 3A. STANDARD 5V LVPECL OUTPUT TERMINATION
5V
PECL
Zo = 50 Ohm
Zo = 50 Ohm
5V
R3
R4
84
84
+
-
R1
R2
125
125
PECL
FIGURE 3B. 5V LVPECL OUTPUT TERMINATION EXAMPLE
IDT^™ / ICS^™ 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
8
ICS853052AG REV. B OCTOBER 24, 2007