ICS844801I-24 Datasheet, PDF (8/13 Pages) Integrated Device Technology – FEMTOCLOCKS™ CRYSTAL-TO-LVDS 400MHZ FREQUENCY SYNTHESIZER

ICS844801I-24
FEMTOCLOCKS™ CRYSTAL-TO-LVDS 400MHZ FREQUENCY SYNTHESIZER
PRELIMINARY
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to
half swing in order to prevent signal interference with the power
rail and to reduce noise. This configuration requires that the output
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50Ω applications, R1
and R2 can be 100Ω. This can also be accomplished by removing
R1 and making R2 50Ω.
VDD
Ro
VDD
Rs
Zo = 50
Zo = Ro + Rs
R1
.1uf
XTAL_I N
R2
XTAL_OUT
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
3.3V, 2.5V LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 4. In a 100Ω
differential transmission line environment, LVDS dr ivers
require a matched load termination of 100Ω across near
the receiver input. For a multiple LVDS outputs buffer, if only
partial outputs are used, it is recommended to terminate the
unused outputs.
VDD
LVDS
3.3V or 2.5V
+
R1
100
-
100 Ω Differential Transmission
FIGURE 4. TYPICAL LVDS DRIVER TERMINATION
IDT^™ / ICS^™ LVDS 400MHZ FREQUENCY SYNTHESIZER
8
ICS844801AGI-24 REV A JANUARY 16, 2008