ICS843301I-108 Datasheet, PDF (8/15 Pages) Integrated Device Technology – FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL 75MHZ FREQUENCY SYNTHESIZER W/SSC

ICS843301I-108
FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER W/SSC
PRELIMINARY
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 5A and 5B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
Z_o = 50Ω
FOUT
FIN
Z_o = 50Ω
50Ω
RTT =
1
((V_OH + V_OL) / (V_CC – 2)) – 2
Z_o
50Ω
V_CC - 2V
RTT
FOUT
3.3V
125Ω
125Ω
Z_o = 50Ω
FIN
Z_o = 50Ω
84Ω
84Ω
FIGURE 5A. LVPECL OUTPUT TERMINATION
FIGURE 5B. LVPECL OUTPUT TERMINATION
IDT^™ / ICS^™ 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER W/SSC 8
ICS843301BGI-108 REV. A OCTOBER 9, 2007