9ZXL0831 Datasheet, PDF (8/18 Pages) Integrated Device Technology – Low-power push-pull outputs

9ZXL0831
8-OUTPUT LOW-POWER BUFFER FOR PCIE GEN1-2-3 AND QPI
Electrical Characteristics–Skew and Differential Jitter Parameters
T_A = T_COM; Supply Voltage V_DD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
CLK_IN, DIF[x:0]
t_{SPO_PLL}
Input-to-Output Skew in PLL mode
nominal value @ 25°C, 3.3V
CLK_IN, DIF[x:0]
t_{PD_BYP}
Input-to-Output Skew in Bypass mode
nominal value @ 25°C, 3.3V
CLK_IN, DIF[x:0]
t_{DSPO_PLL}
Input-to-Output Skew Varation in PLL mode
across voltage and temperature
MIN
-100
2.5
-50
TYP
-60
3.2
MAX
100
4.5
50
UNITS NOTES
ps 1,2,4,5,8
ns 1,2,3,5,8
ps 1,2,3,5,8
CLK_IN, DIF[x:0]
Input-to-Output Skew Varation in Bypass mode
t_{DSPO_BYP}
across voltage and temperature
-250
250
ps 1,2,3,5,8
CLK_IN, DIF[x:0]
t_DTE
Random Differential Tracking error beween two
9ZX devices in Hi BW Mode
1
5
ps _1,2,3,5,8
(rms)
CLK_IN, DIF[x:0]
Random Differential Spread Spectrum Tracking
t_{DSSTE error beween two 9ZX devices in Hi BW Mode}
5
75
ps 1,2,3,5,8
DIF{x:0]
t_{SKEW_ALL}
Output-to-Output Skew across all outputs
(Common to Bypass and PLL mode)
53
65
ps 1,2,3,8
PLL Jitter Peaking
j_peak-hibw
LOBW#_BYPASS_HIBW = 1
0
1.2
2.5
dB
7,8
PLL Jitter Peaking
j_peak-lobw
LOBW#_BYPASS_HIBW = 0
0
0.76
2
dB
7,8
PLL Bandwidth
pll_HIBW
LOBW#_BYPASS_HIBW = 1
2
3
4
MHz
8,9
PLL Bandwidth
pll_LOBW
LOBW#_BYPASS_HIBW = 0
0.7
1.1
1.4
MHz
8,9
Duty Cycle
t_DC
Duty Cycle Distortion
t_DCD
Measured differentially, PLL Mode
Measured differentially, Bypass Mode
@100MHz
45
50.1
55
-2
0
2
%
1
%
1,10
Jitter, Cycle to cycle
t_jcyc-cyc
PLL mode
Additive Jitter in Bypass Mode
34
50
ps
1,11
17
50
ps
1,11
Notes for preceding table:
1 _{CL = 2pF with RS = 27Ω for Zo = 85Ω differential trace impedance. Input to output skew is measured at the first output edge following the}
corresponding input.
2 _{Measured from differential cross-point to differential cross-point. This parameter can be tuned with external feedback path, if present.}
3 _{All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it.}
4 _{This parameter is deterministic for a given device}
5 _{Measured with scope averaging on to find mean value.}
6._{t is the period of the input clock}
7 _{Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking.}
8. _{Guaranteed by design and characterization, not 100% tested in production.}
9 _{Measured at 3 db down or half power point.}
10 _{Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.}
11 _{Measured from differential waveform}
IDT® 8-OUTPUT LOW-POWER BUFFER FOR PCIE GEN1-2-3 AND QPI
8
9ZXL0831
REV C 070115