9FGV0241_16 Datasheet, PDF (8/15 Pages) Integrated Device Technology – 2-OUTPUT VERY LOW POWER PCIE GEN1/2/3 CLOCK GENERATOR

9FGV0241
2-OUTPUT VERY LOW POWER PCIE GEN1/2/3 CLOCK GENERATOR
Electrical Characteristics–REF
TA = T_COM or T_IND; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
Long Accuracy
ppm
see Tperiod min-max values
0
Clock period
T_period
25 MHz output nominal
40
Rise/Fall Slew Rate
t_rf1
Byte 3 = 1F, V_OH = VDD-0.45V, V_OL = 0.45V
0.5
1
2.5
Rise/Fall Slew Rate
t_rf1
Byte 3 = 5F, V_OH = VDD-0.45V, V_OL = 0.45V
0.5
1.6
2.5
Rise/Fall Slew Rate
t_rf1
Byte 3 = 9F, V_OH = VDD-0.45V, V_OL = 0.45V
0.5
2
2.5
Rise/Fall Slew Rate
t_rf1
Byte 3 = DF, V_OH = VDD-0.45V, V_OL = 0.45V
0.5
2.1
2.5
Duty Cycle
d_t1
V_T = VDD/2 V
45
53.1
55
Duty Cycle Distortion
d_tcd
V_T = VDD/2 V
0
2
4
Jitter, cycle to cycle
t_jcyc-cyc
V_T = VDD/2 V
19
250
Noise floor
t_jdBc1k
1kHz offset
-130
-105
Noise floor
t_jdBc10k
10kHz offset to Nyquist
-140
-120
Jitter, phase
t_jphREF
12kHz to 5MHz
0.63
1.5
1_{Guaranteed by design and characterization, not 100% tested in production.}
2 _{All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is trimmed to 25.00 MHz}
3 _{Typical value occurs when REF slew rate is set to default value}
4 _{When driven by a crystal.}
5 _{When driven by an external oscillator via the X1 pin. X2 should be floating in this case.}
UNITS
ppm
ns
V/ns
V/ns
V/ns
V/ns
%
%
ps
dBc
dBc
ps
(rms)
Notes
1,2
1,2
1,3
1,3
1,3
1,3
1,4
1,5
1,4
1,4
1,4
1,4
Clock Periods–Differential Outputs with Spread Spectrum Disabled
SSC OFF
DIF
Center
Freq.
MHz
100.00
Measurement Window
1 Clock
1us
0.1s
0.1s
0.1s
-c2c jitter
-SSC
- ppm
AbsPer ^{Short-Term Long-Term}
Min
Average Average
Min
Min
0 ppm
Period
Nominal
+ ppm
Long-Term
Average
Max
9.94900
9.99900 10.00000 10.00100
1us
+SSC
Short-Term
Average
Max
1 Clock
+c2c jitter Units Notes
AbsPer
Max
10.05100 ns 1,2
Clock Periods–Differential Outputs with -0.5% Spread Spectrum Enabled
SSC ON
DIF
Center
Freq.
MHz
99.75
Measurement Window
1 Clock
1us
0.1s
0.1s
0.1s
-c2c jitter
-SSC
- ppm
AbsPer
Min
Short-Term Long-Term
Average Average
Min
Min
0 ppm
Period
Nominal
+ ppm
Long-Term
Average
Max
9.94906 9.99906 10.02406 10.02506 10.02607
1us
+SSC
Short-Term
Average
Max
10.05107
1 Clock
+c2c jitter Units Notes
AbsPer
Max
10.10107 ns 1,2
1_{Guaranteed by design and characterization, not 100% tested in production.}
2 _{All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is trimmed to 25.00 MHz}
IDT® 2-OUTPUT VERY LOW POWER PCIE GEN1/2/3 CLOCK GENERATOR
8
9FGV0241 OCTOBER 18, 2016