84329-01_14 Datasheet, PDF (8/20 Pages) Integrated Device Technology – 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

84329-01
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply
pins are vulnerable to random noise. The 84329-01
provides separate power supplies to isolate any high
switching noise from the outputs to the internal PLL. V_CC
and V_CCA should be individually connected to the power
supply plane through vias, and bypass capacitors
should be used for each pin. To achieve optimum jitter
performance, power supply isolation is required. Figure 2
illustrates how a 10Ω resistor along with a 10μF and
a .01μF bypass capacitor should be connected to each
V_CCA pin.
V
CC
V_CCA
3.3V
.01μF 10Ω
.01μF 10 μF
FIGURE 2. POWER SUPPLY FILTERING
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs.Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion. Figures 3A and 3B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 3B. LVPECL OUTPUT TERMINATION
84329AM-01
www.idt.com
8
REV. D APRIL 9, 2014