843081I-01 Datasheet, PDF (8/16 Pages) Integrated Device Technology – FemtoClock® Crystal-to-2.5V, 3.3V LVPECL Clock Multiplier

843081I-01 DATA SHEET
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed
to drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion. Figures 3A and 3B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 3B. LVPECL OUTPUT TERMINATION
FEMTOCLOCKS^® CRYSTAL-TO-
8
3.3V, 2.5V LVPECL CLOCK MULTIPLIER
REVISION C 11/5/15