8312I_15 Datasheet, PDF (8/18 Pages) Integrated Device Technology – Low Skew, 1-to-12 LVCMOS/LVTTL Fanout Buffer

8312I Datasheet
Table 5C. AC Characteristics, V_DD = V_DDO = 1.8V ± 0.2V, T_A = -40°C to 85°C
Parameter Symbol
Test Conditions
f_MAX
tp_LH
tjit
Output Frequency
Propagation Delay, Low to High; NOTE 1
Buffer Additive Phase Jitter, RMS; refer to
Additive Phase Jitter Section
ƒ  200MHz
100MHz, Integration Range:
12kHz – 20MHz
tsk(o)
Output Skew; NOTE 2, 5
tsk(pp)
Part-to-Part Skew; NOTE 3, 5
t_R / t_F
odc
Output Rise/Fall Time; NOTE 5
Output Duty Cycle
20% to 80%
ƒ  100MHz
Minimum Typical Maximum Units
200
MHz
1.6
3.3
4.9
ns
0.172
ps
160
ps
2.4
ns
175
875
ps
45
55
%
All parameters measured at f_MAX unless noted otherwise.
NOTE 1: Measured from the V_DD/2 of the input to V_DDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V_DDO/2.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions.
Using the same type of input on each device, the output is measured at V_DDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
Table 5D. AC Characteristics, V_DD = 3.3V ± 5%, V_DDO = 2.5V ± 5%, T_A = -40°C to 85°C
Parameter Symbol
Test Conditions
Minimum Typical Maximum Units
f_MAX
tp_LH
tjit
Output Frequency
250
MHz
Propagation Delay, Low to High; NOTE 1
ƒ  250MHz
1.5
2.1
2.8
ns
Buffer Additive Phase Jitter, RMS; refer to
Additive Phase Jitter Section
100MHz, Integration Range:
12kHz – 20MHz
0.045
ps
tsk(o)
Output Skew; NOTE 2, 5
150
ps
tsk(pp)
Part-to-Part Skew; NOTE 3, 5
1
ns
t_R / t_F
odc
Output Rise/Fall Time; NOTE 5
Output Duty Cycle
20% to 80%
200
ƒ  150MHz
45
800
ps
55
%
All parameters measured at f_MAX unless noted otherwise.
NOTE 1: Measured from the V_DD/2 of the input to V_DDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V_DDO/2.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions.
Using the same type of input on each device, the output is measured at V_DDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
©2015 Integrated Device Technology, Inc
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December 14, 2015