82P33810_17 Datasheet, PDF (8/11 Pages) Integrated Device Technology – Synchronization Management Unit for IEEE 1588 and 10G/40G/100G Synchronous Ethernet

82P33810 Datasheet
Table 1: Pin Description (Continued)
Pin No.
F1
K3
G1
L3
L5
C1, C6, C7, D2, F2, F9,
G2, H2, K1, K2
A5, A7, B2, B3, L4, M4
E4, E6, L7, M8
D5,F7
L10, H12
B9, C2, D1, D6, D7, E2,
E8, F3, F8, H3, L1, L2
B1, B4, B5, B7, K4, M3
E7, F4, K7, M7
D4, F6, H11, L9
D3
C3, F5, G4, G5, G6, G8,
H4, H5, H6, H7, H8, J3,
J4, J5, J6, J7, J8
A1, A2, A3, A4, A10,
A12, B10, B12, E3, G3,
G7, L6
Name
TMS
TRSTB
TCK
TDI
TDO
VDDA
VDDAO
VDDDO
VDDD
VDDD_1_8
VSSA
VSSAO
VSSDO
VSSD
VSSCOM
VSS
IC
I/O
I
pull-up
I
pull-up
I
pull-down
I
pull-up
O
tri-state
Power
Power
Power
Power
Power
Ground
Ground
Ground
Ground
Ground
Ground
-
Type
Description
JTAG (per IEEE 1149.1)
CMOS
CMOS
CMOS
CMOS
CMOS
-
TMS: JTAG Test Mode Select
The signal on this pin controls the JTAG test performance and is sampled on the rising edge
of TCK.
TRSTB: JTAG Test Reset (Active Low)
A low signal on this pin resets the JTAG test port.
This pin should be connected to ground when JTAG is not used.
TCK: JTAG Test Clock
The clock for the JTAG test is input on this pin. TDI and TMS are sampled on the rising edge
of TCK and TDO is updated on the falling edge of TCK.
If TCK is idle at a low level, all stored-state devices contained in the test logic will indefinitely
retain their state.
TDI: JTAG Test Data Input
The test data are input on this pin. They are clocked into the device on the rising edge of
TCK.
TDO: JTAG Test Data Output
The test data are output on this pin. They are clocked out of the device on the falling edge of
TCK.
TDO pin outputs a high impedance signal except during the process of data scanning.
Power & Ground
VDDA: Analog Core Power - +3.3V DC nominal
VDDAO: Analog Output Power - +3.3V DC nominal
VDDDO: Digital Output Power - +3.3V DC nominal
VDDD: Digital Core Power - +3.3V DC nominal
VDDD_1_8: Digital Core Power - +1.8V DC nominal
-
VSSA: Ground
VSSAO: Ground
VSSDO: Ground
VSSD: Ground
-
VSSCOM: Ground
VSS: Ground
-
Other
IC: Internal Connection
-
Internal Use. This pin must be left open for normal operation.
2.1 RECOMMENDATIONS FOR UNUSED INPUT
AND OUTPUT PINS
2.1.1
INPUTS
Control Pins
All control pins have internal pull-ups or pull-downs; additional resis-
tance is not required but can be added for additional protection. A 1kΩ
resistor can be used.
Single-Ended Clock Inputs
For protection, unused single-ended clock inputs should be tied to
ground.
Differential Clock Inputs
For applications not requiring the use of a differential input, both
*_POS and *_NEG can be left floating. Though not required, but for
additional protection, a 1kΩ resistor can be tied from _POS to ground.
©2017 Integrated Device Technology, Inc.
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Revision 7, December 22, 2016