7204L50P Datasheet, PDF (8/14 Pages) Integrated Device Technology – First-In/First-Out Dual-Port memory

IDT7203/7204/7205/7206/7207/7208 CMOS ASYNCHRONOUS FIFO
2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9, 65,536 x 9
COMMERCIAL, INDUSTRIAL AND MILITARY
TEMPERATURE RANGES
IGNORED
LAST READ
READ
FIRST WRITE
W
R
EF
DATA ^OUT
tREF
tWEF
tA
VALID
Figure 5. Empty Flag Timing From Last Read to First Write
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RT
W,R
HF, EF, FF
tRTC
tRT
tRTS
tRTF
NOTE:
1. EF, FF and HF may change status during Retransmit, but flags will be valid at tRTC.
Figure 6. Retransmit
tRTR
FLAG VALID
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W
tWEF
EF
tRPE
R
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Figure 7. Minimum Timing for an Empty Flag Coincident Read Pulse.
R
tRFF
FF
tWPF
W
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Figure 8. Minimum Timing for a Full Flag Coincident Write Pulse.
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