7202LA20JG Datasheet, PDF (8/14 Pages) Integrated Device Technology – CMOS ASYNCHRONOUS FIFO

IDT7201L/7201LA/7202LA CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1,024 x 9
LAST READ
IGNORED
READ
FIRST WRITE
W
COMMERCIAL, INDUSTRIAL AND MILITARY
TEMPERATURE RANGES
ADDITIONAL FIRST READ
WRITES
R
EF
DATA OUT
tREF
tWEF
tA
VALID
VALID
Figure 5. Empty Flag From Last Read to First Write
2679 drw 07
RT
W,R
HF, EF, FF
tRTC
tRT
tRTS
tRTF
Figure 6. Retransmit
tRTR
FLAG VALID
2679 drw 08
W
tWEF
EF
tRPE
R
2679 drw 09
Figure 7. Minimum Timing for an Empty Flag Coincident Read Pulse
R
tRFF
FF
tWPF
W
2679 drw 10
Figure 8. Minimum Timing for a Full Flag Coincident Write Pulse
8