IDT82P5088_14 Datasheet, PDF (79/82 Pages) Integrated Device Technology – Universal Octal T1/E1/J1 LIU with Integrated Clock Adapter

IDT82P5088
UNIVERSAL OCTAL T1/E1/J1 LIU WITH INTEGRATED CLOCK ADAPTER
CS+RD
A[x:0]
READ D[7:0]
tRC
tRDW
tRecovery
tAH
tAV
Valid Address
tPRD
tDAZ
Valid Data
Note: The WR pin should be tied to high.
7.2.2 Write Cycle Specification
Figure-34 Intel Non-Multiplexed Mode Read Cycle
Symbol
tWC
tWRW
tAV
tAH
tDV
tDHW
tRecovery
Parameter
Write Cycle Time
Valid WR width
Delay from WR to Valid Address
Address to WR Hold Time
Delay from WR to valid write data
Write Data to WR Hold Time
Recovery Time from Write Cycle
Min
Max
Units
237
ns
232
ns
21
ns
165
ns
83
ns
165
ns
5
ns
WR+CS
A[x:0]
Write D[7:0]
tWC
tWRW
tRecovery
tAH
tAV
Valid Address
tDHW
tDV
Valid Data
Note: The RD pin should be tied to high.
Figure-35 Intel Non-Multiplexed Mode Write Cycle
MICROCONTROLLER INTERFACE TIMING
79
July 30, 2014