IDT82V3380A Datasheet, PDF (72/177 Pages) Integrated Device Technology – SYNCHRONOUS ETHERNET IDT WAN PLL™

IDT82V3380A
SYNCHRONOUS ETHERNET WAN PLL™
INPUT_MODE_CNFG - Input Mode Configuration
Address: 09H
Type: Read / Write
Default Value: 10100XX0
7
6
5
AUTO_EXT_SY
NC_EN
EXT_SYNC_EN
PH_ALARM_TI
MEOUT
4
SYNC_FREQ1
3
SYNC_FREQ0
2
1
0
IN_SONET_SD MASTER_SLAV REVERTIVE_M
H
E
ODE
Bit
Name
Description
7
AUTO_EXT_SYNC_EN Refer to the description of the EXT_SYNC_EN bit (b6, 09H).
This bit, together with the AUTO_EXT_SYNC_EN bit (b7, 09H), determines whether EX_SYNC1 is enabled to synchronize
the frame sync output signals.
AUTO_EXT_SYNC_EN EXT_SYNC_EN
6
EXT_SYNC_EN
don’t-care
0
Synchronization
Disabled (default)
0
1
Enabled
1
1
Enabled if the T0 selected input clock is IN11; otherwise, disabled.
This bit determines how to clear the phase lock alarm.
0: The phase lock alarm will be cleared when a ‘1’ is written to the corresponding INn_PH_LOCK_ALARM bit (b4/0,
5
PH_ALARM_TIMEOUT 43H~49H).
1: The phase lock alarm will be cleared after a period (= TIME_OUT_VALUE[5:0] (b5~0, 08H) X MULTI_FACTOR[1:0]
(b7~6, 08H) in second) which starts from when the alarm is raised. (default)
These bits set the frequency of the frame sync signal input on the EX_SYNC1 pin.
00: 8 kHz (default)
4-3
SYNC_FREQ[1:0] 01: 8 kHz.
10: 4 kHz.
11: 2 kHz.
This bit selects the SDH or SONET network type.
0: SDH. The DPLL required clock is 2.048 MHz when the IN_FREQ[3:0] bits (b3~0, 14H~17H & 19H~22H) are ‘0001’; the
2
IN_SONET_SDH
T0/T4 DPLL output from the 16E1/16T1 path is 16E1; and OUT9 outputs a 2.048 MHz signal if enabled.
1: SONET. The DPLL required clock is 1.544 MHz when the IN_FREQ[3:0] bits (b3~0, 14H~17H & 19H~22H) are ‘0001’; the
T0/T4 DPLL output from the 16E1/16T1 path is 16T1; and OUT9 outputs a 1.544 MHz signal if enabled.
The default value of this bit is determined by the SONET/SDH pin during reset.
1
MASTER_SLAVE
This bit is read only. It indicates the value of the MS/SL pin.
Its default value is determined by the MS/SL pin during reset.
This bit selects Revertive or Non-Revertive switch for T0 path.
0
REVERTIVE_MODE 0: Non-Revertive switch. (default)
1: Revertive switch.
Programming Information
72
May 16, 2011