IDT82P2288 Datasheet, PDF (71/384 Pages) Integrated Device Technology – Octal T1/E1/J1 Long Haul Short Haul Transceiver

IDT82P2288
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
3.17.2 E1 MODE
In E1 mode, the Receive System Interface can be set in Non-multi-
plexed Mode or Multiplexed Mode. In the Non-multiplexed Mode, the
RSDn pin is used to output the received data from each link at the bit
rate of 2.048 Mb/s. While in the Multiplexed Mode, the received data
from the eight links is byte interleaved to form two high speed data
streams and output on the MRSDA1 (MRSDB1) and MRSDA2
(MRSDB2) pins at the bit rate of 8.192 Mb/s.
In the Non-multiplexed Mode, if the receive system interface and
the receive line side are timed to a same clock source, the Receive Sys-
tem Interface is in Receive Clock Master mode. If the receive system
interface and the receive line side are timed to different clock sources,
the Receive System Interface is in Receive Clock Slave mode.
In the Receive Clock Master mode, if RSCKn outputs pulses during
the entire E1 frame, the Receive System Interface is in Receive Clock
Master Full E1 mode. If only the clocks aligned to the selected timeslots
are output on RSCKn, the Receive System Interface is in Receive Clock
Master Fractional E1 mode.
Table 40 summarizes how to set the receive system interface of
each link into various operating modes and the pins’ direction of the
receive system interface in different operating modes.
Table 40: Operating Modes Selection In E1 Receive Path
RMUX RMODE G56K, GAP
Operating Mode
Input
Receive System Interface Pin
Output
00 Receive Clock Master Full E1
0
0
not both 0s ^{1 Receive Clock Master Fractional E1}
X
RSCKn, RSFSn, RSDn, RSIGn
1
X
Receive Clock Slave
RSCKn, RSFSn
RSDn, RSIGn
1
X
X
Receive Multiplexed
MRSCK, MRSFS _{MRSDA[1:2], MRSIGA[1:2] (MRSDB[1:2], MRSIGB[1:2])} ²
NOTE:
1. When the G56K, GAP bits in RPLC indirect registers are set, the PCCE bit must be set to ‘1’.
2. In Receive Multiplexed mode, two sets of multiplexed data and signaling pins (A and B) are provided. Their functions are the same. One is the backup for the other.
3.17.2.1 Receive Clock Master Mode
In the Receive Clock Master mode, each link uses its own timing
signal on the RSCKn pin and framing pulse on the RSFSn pin to output
the data on each RSDn pin. The signaling bits on the RSIGn pin are per-
timeslot aligned with the data on the RSDn pin.
In the Receive Clock Master mode, the data on the system inter-
face is clocked by the RSCKn. The active edge of the RSCKn used to
update the pulse on the RSFSn is determined by the FE bit. The active
edge of the RSCKn used to update the data on the RSDn and RSIGn is
determined by the DE bit. If the FE bit and the DE bit are not equal, the
pulse on the RSFSn is ahead.
In the Receive Clock Master mode, the RSFSn can indicate the
Basic frame, CRC Multi-frame, Signaling Multi-frame, or both the CRC
Multi-frame and Signaling Multi-frame, or the TS1 and TS 16 overhead.
All the indications are selected by the OHD bit, the SMFS bit and the
CMFS bit. The active polarity of the RSFSn is selected by the FSINV bit.
The Receive Clock Master mode includes two sub-modes: Receive
Clock Master Full E1 mode and Receive Clock Master Fractional E1
mode.
3.17.2.1.1 Receive Clock Master Full E1 Mode
Besides all the common functions described in the Receive Clock
Master mode, the special feature in this mode is that the RSCKn is a
standard 2.048 MHz clock, and the data in all 32 timeslots in a standard
E1 frame is clocked out by the RSCKn.
3.17.2.1.2 Receive Clock Master Fractional E1 Mode
Besides all the common functions described in the Receive Clock
Master mode, the special feature in this mode is that the RSCKn is a
gapped 2.048 MHz clock (no clock signal during the selected timeslot).
The RSCKn is gapped during the timeslots or the Bit 8 duration by
selecting the G56K & GAP bits in the Receive Payload Control. The data
in the corresponding gapped duration is a don't care condition.
3.17.2.2 Receive Clock Slave Mode
In the Receive Clock Slave mode, the timing signal on the RSCKn
pin and framing pulse on the RSFSn pin to output the data on the RSDn
pin are provided by the system side. When the RSLVCK bit is set to ‘0’,
each link uses its own RSCKn and RSFSn; when the RSLVCK bit is set
to ‘1’ and all eight links are in the Receive Clock Slave mode, the eight
links use the RSCK[1] and RSFS[1] to output the data. The signaling bits
on the RSIGn pin are per-timeslot aligned with the data on the RSDn
pin.
In the Receive Clock Slave mode, the data on the system interface
is clocked by the RSCKn. The active edge of the RSCKn used to sample
the pulse on the RSFSn is determined by the FE bit. The active edge of
the RSCKn used to update the data on the RSDn and RSIGn is deter-
mined by the DE bit. If the FE bit and the DE bit are not equal, the pulse
on the RSFSn is ahead. The speed of the RSCKn can be selected by
the CMS bit to be the same rate as the data rate on the system side
(2.048 MHz) or double the data rate (4.096 MHz). If all eight links use
the RSCK[1] and RSFS[1] to output the data, the CMS bit of the eight
links should be set to the same value. If the speed of the RSCKn is dou-
ble the data rate, there will be two active edges in one bit duration. In
this case, the EDGE bit determines the active edge to update the data
Functional Description
60
March 22, 2004