IDT8V44N003I Datasheet, PDF (7/28 Pages) Integrated Device Technology – Buffered copy of input reference clock at LVDS output levels

IDT8V44N003I Data Sheet
Table 3C. Input Divider P Coding
Register Bit
P_n2
P_n1
P_n0
0
0
0
0
0
1
0
1
0
0
1
1
1
X
X
Input Divider P
1
2
4
8
0.5
FEMTOCLOCK^® NG LVDS CLOCK SYNTHESIZER
Table 3D. PLL Post Divider N Coding
Register Bit
N_n[6:0]
000000X
Frequency Divider N
2
0000010
2
0000011
3
0000100
4
0000101
5
000011X
6
000100X
8
000101X
10
000110X
12
000111X
14
001000X
16
...
N (even integer)
111101X
124
111111X
126
NOTE: “X” can be either 0 or 1 (don’t care).
Output Frequency Range
f_OUT,MIN (MHz)
990
f_OUT,MAX (MHz)
1275
990
1275
660
850
495
637.5
396
510
330
425
247.5
318.75
198
255
165
212.5
141.4286
182.143
123.75
159.375
(1980 ÷ N)
(2550 ÷ N)
15.96774
20.565
15.71429
20.238
IDT8V44N003NLGI REVISION A APRIL 24, 2012
7
©2012 Integrated Device Technology, Inc.