IDT5T9891 Datasheet, PDF (7/37 Pages) Integrated Device Technology – EEPROM PROGRAMMABLE 2.5V PROGRAMMABLE SKEW PLL DIFFERENTIAL CLOCK DRIVER

IDT5T9891
EEPROM PROGRAMMABLE 2.5V PROGRAMMABLE SKEW PLL DIFFERENTIAL
INDUSTRIAL TEMPERATURE RANGE
JTAG/ I²C SERIAL DESCRIPTION, CONT.
Bit
Description
21 Skew or frequency selection for bank 2
20 Skew or frequency selection for bank 2
19 Skew or frequency selection for bank 3
18 Skew or frequency selection for bank 3
17 Skew or frequency selection for bank 3
16 Skew or frequency selection for bank 3
15 Skew or frequency selection for bank 3
14 Skew or frequency selection for bank 4
13 Skew or frequency selection for bank 4
12 Skew or frequency selection for bank 4
11 Skew or frequency selection for bank 4
10 Skew or frequency selection for bank 4
9 Skew or frequency selection for bank 5
8 Skew or frequency selection for bank 5
7 Skew or frequency selection for bank 5
6 Skew or frequency selection for bank 5
5 Skew or frequency selection for bank 5
4 Skew or frequency selection for FB bank
3 Skew or frequency selection for FB bank
2 Skew or frequency selection for FB bank
1 Skew or frequency selection for FB bank
0 Skew or frequency selection for FB bank
JTAG/ I²C SERIAL CONFIGURATIONS:
OUTPUT ENABLE/DISABLE
Bit 59 (OMODE) Bit 56-52 (nsOE)
Output
X (X)
0 and (L)
Normal Operation
0 and (L)
1 or (H)
Tri-Sate
1 or (H)
1 or (H)
Gated⁽¹⁾
NOTE:
1. OMODE and its corresponding Bit 59 selects whether the outputs are gated LOW/
HIGH or tri-stated. When OMODE is HIGH or the corresponding Bit 59 is 1, the outputs'
disable state will be gated. Bit 58 determines the level at which the outputs stop.
When Bit 58 is 0/ 1, the nQ and QFB are stopped in a HIGH/LOW state, while the
nQ and QFB are stopped in a LOW/HIGH state. When OMODE is LOW and its
corresponding Bit 59 is 0, the outputs' disable state will be the tri-state.
JTAG/ I²C SERIAL CONFIGURATIONS:
POWERDOWN
PD
Bit 59 (OMODE)
Output
H
X (X)
Normal Operation
L
0 and (L)
Tri-Sate
L
1 or (H)
Gated⁽¹⁾
NOTE:
1. OMODE and its corresponding Bit 59 selects whether the outputs are gated LOW/
HIGH or tri-stated. When OMODE is HIGH or the corresponding Bit 59 is 1, the outputs'
disable state will be gated. Bit 58 determines the level at which the outputs stop.
When Bit 58 is 0/ 1, the nQ and QFB are stopped in a HIGH/LOW state, while the nQ
and QFB are stopped in a LOW/HIGH state. When OMODE is LOW and its
corresponding Bit 59 is 0, the outputs' disable state will be the tri-state.
JTAG/ I²C SERIAL CONFIGURATIONS:
CLOCK INPUT INTERFACE SELEC-
TION⁽¹⁾
Bit 31, 33, 35
Bit 30, 32, 34
Interface
0
0
Differential⁽²⁾
0
1
2.5V LVTTL
1
1
1.8V LVTTL
NOTES:
1. All other states that are undefined in the table will be reserved.
2. Differential input interface for HSTL/eHSTL, LVEPECL (2.5V), and 2.5V/1.8V LVTTL.
JTAG/ I²C SERIAL CONFIGURATIONS:
OUTPUT DRIVE STRENGTH
SELECTION⁽¹⁾
Bit 37, 39, 41,
Bit 36, 38, 40,
43, 45, 47
42, 44, 46
Interface
0
0
2.5V LVTTL
0
1
1.8V LVTTL
1
0
HSTL/eHSTL
NOTE:
1. All other states that are undefined in the table will be reserved.
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