IDT5993A Datasheet, PDF (7/8 Pages) Integrated Device Technology – PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK

IDT5993A
PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
AC TIMING DIAGRAM
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
REF
tPD
tREF
tRPWH
tRPWL
tODCV
tODCV
FB
Q
OTHER Q
tSKEWPR
tSKEW0, 1
tJR
tSKEWPR
tSKEW0, 1
REF DIVIDED BY 2
tSKEW3, 4
tSKEW1, 3, 4
tSKEW3
tSKEW3
tSKEW2
REF DIVIDED BY 4
NOTES:
VCCQ/PE: The AC Timing Diagram applies to VCCQ/PE=VCC. For VCCQ/PE=GND, the negative edge of FB aligns with the negative edge of REF, divided outputs change on the
negative edge of REF, and the positive edges of the divide-by-2 and the divide-by-4 signals align.
Skew:
The time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with 50pF (30pF for
-2 and -5) and terminated with 50Ω to 2.06V.
tSKEWPR: The skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU.
tSKEW0:
tDEV:
The skew between outputs when they are selected for 0tU_.
The output-to-output skew between any two devices operating under the same conditions (VCC, ambient temperature, air flow, etc.)
tODCV: The deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications.
tPWH is measured at 2V.
tPWL is measured at 0.8V.
tORISE and tOFALL are measured between 0.8V and 2V.
tLOCK:
The time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is measured
from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
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