9FGV0431_16 Datasheet, PDF (7/15 Pages) Integrated Device Technology – 4-OUTPUT VERY LOW POWER PCIE GEN1-2-3 CLOCK GENERATOR

9FGV0431
4-OUTPUT VERY LOW POWER PCIE GEN1-2-3 CLOCK GENERATOR
Electrical Characteristics–DIF 0.7V Low Power HCSL Output
TA = T_COM or T_IND; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
Slew rate
Slew rate matching
SYMBOL
Trf
ΔTrf
CONDITIONS
Scope averaging on 3.0V/ns setting
Scope averaging on 2.0V/ns setting
Slew rate matching, Scope averaging on
MIN TYP MAX UNITS NOTES
2.6 3.5 4.6 ^V/ns 1, 2, 3
1.5 2.5 3.5 V/ns 1, 2, 3
8
20
% 1,2,4
Voltage High
Voltage Low
V_HIGH
V_LOW
Statistical measurement on single-ended signal _{660 797 850}
1,8
using oscilloscope math function. (Scope
mV
averaging on)
-150 15 150
1
Max Voltage
Min Voltage
Vswing
Crossing Voltage (abs)
Crossing Voltage (var)
Vmax
Vmin
Vswing
Vcross_abs
Δ-Vcross
Measurement on single ended signal using
absolute value. (Scope averaging off)
Scope averaging off
Scope averaging off
Scope averaging off
-300
833
-41
1150
mV
1
1
300 ¹⁵⁶⁴
mV 1,2
300 427 550 mV 1,5
15 140 mV 1,6
1_{Guaranteed by design and characterization, not 100% tested in production. CL = 2pF with RS = 33Ω for Zo = 50Ω (100Ω differential}
trace impedance).
2 _{Measured from differential waveform}
3 _{Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around}
differential 0V.
4 _{Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on}
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5 _{Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising}
edge (i.e. Clock rising and Clock# falling).
6 _{The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross}
absolute) allowed. The intent is to limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute.
7 _{At default SMBus settings.}
Electrical Characteristics–Phase Jitter Parameters
TA = T_COM or T_IND; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
INDUSTRY
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX LIMIT UNITS NOTES
t_jphPCIeG1
PCIe Gen 1
20 25 35
86
ps _1,2,3,5
(p-p)
Phase Jitter, PCI Express t_jphPCIeG2
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
0.8 0.9 1.1
1.5 1.6 1.9
3
ps _1,2,5
(rms)
3.1
ps _1,2,5
(rms)
t_jphPCIeG3
PCIe Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz)
0.34 0.38 0.50
1
ps
(rms) ^1,2,4,5
1 _{Guaranteed by design and characterization, not 100% tested in production.}
2 _{See http://www.pcisig.com for complete specs}
3 _{Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.}
4 _{Calculated from Intel-supplied Clock Jitter Tool}
5 _{Applies to all differential outputs}
IDT® 4-OUTPUT VERY LOW POWER PCIE GEN1-2-3 CLOCK GENERATOR
7
9FGV0431 OCTOBER 18, 2016