9E4101AFILF Datasheet, PDF (7/19 Pages) Integrated Device Technology – Programmable Timing Control HubTM for Intel Systems

ICS9E4101
Programmable Timing Control Hub^TM for Intel Systems
I²C Table: Output Control Register
Byte 5
Pin #
Name
Bit 7
19,20,22,23,
24,25,26,27,30,31,
32,33,35,36
SRC Stop Drive Mode
Bit 6
Bit 5
Bit 4
Bit 3
19,20,22,23,
24,25,26,27,30,31,
32,33,35,36
SRC PD Drive Mode
Bit 2
Bit 1
Bit 0
35,36
40,41
43,44
CPUCLK_ITP
CPUCLK1
CPUCLK0
Control Function
Drive Mode in
PCI_Stop
Type
RW
RESERVED
RESERVED
RESERVED
Drive Mode in PD
RW
Drive Mode in PD
RW
Drive mode in PD
RW
Drive mode in PD
RW
0
Driven
Driven
Driven
Driven
Driven
1
PWD
Hi-Z
0
0
0
0
Hi-Z
0
Hi-Z
0
Hi-Z
0
Hi-Z
0
I²C Table: Output Control Register
Byte 6
Pin #
Name
Bit 7
-
Test Mode Selection
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
52
17,18,19,20,22,23,
24,25,26,27,30,31,
32,33,35,36
54,55,56,3,4,5,8,9,
10
-
-
-
Test Clock Mode Entry
REFOUT Strength
PCI/SRC_STOP
FS_C
FS_B
FS_A
Control Function
Test Mode
Selection
Test Mode
RESERVED
Strength Prog
Type
RW
RW
RW
Stop all PCI and
SRC clocks
RW
readback
R
readback
R
readback
R
0
1
PWD
Hi-Z
REF/N
0
Disable
Enable
1X
2X
Enabled, all _{Disabled, all}
stoppable PCI _{stoppable PCI}
and SRC _{and SRC clocks}
clocks are
are running
stopped.
-
-
-
-
-
-
0
0
1
1
LATCHED
LATCHED
LATCHED
I²C Table: Vendor & Revision ID Register
Byte 7
Pin #
Name
Bit 7
-
RID3
Bit 6
-
RID2
Bit 5
-
RID1
Bit 4
-
RID0
Bit 3
-
VID3
Bit 2
-
VID2
Bit 1
-
VID1
Bit 0
-
VID0
Control Function Type
0
R
-
REVISION ID
R
-
R
-
R
-
R
-
VENDOR ID
R
-
R
-
R
-
1
PWD
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
1
I²C Table: Byte Count Register
Byte 8
Pin #
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
Name
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
Control Function Type
0
RW
-
Writing to this
RW
-
register will
RW
-
configure how
RW
-
many bytes will be _RW
-
read back, default
RW
-
is 08 = 8 bytes.
RW
-
RW
-
1
PWD
-
0
-
0
-
0
-
0
-
1
-
0
-
0
-
0
IDT^TM Programmable Timing Control Hub^TM for Intel Systems
7
1408A—01/25/10