83905I Datasheet, PDF (7/21 Pages) Integrated Device Technology – LVCMOS/ LVTTL Fanout Buffer

83905I Datasheet
AC Electrical Characteristics
Table 6A. AC Characteristics, V_DD = V_DDO = 3.3V ± 5%, T_A = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Using External Crystal
10
f_MAX
Output Frequency _{Using External Clock}
Source NOTE 1
DC
odc
Output Duty Cycle
48
tsk(o) Output Skew; NOTE 2, 3
tjit(Ø) RMS Phase Jitter (Random); NOTE 4
25MHz, Integration Range:
100Hz – 1MHz
t_R / t_F
t_EN
Output Rise/Fall Time
Output Enable
Time; NOTE 5
ENABLE1
ENABLE2
20% to 80%
200
t_DIS
Output Disable
Time; NOTE 5
ENABLE1
ENABLE2
Typical
0.13
Maximum Units
40
MHz
100
MHz
52
%
80
ps
ps
800
ps
4
cycles
4
cycles
4
cycles
4
cycles
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
NOTE: All parameters measured at ƒ  f_MAX using a crystal input unless noted otherwise.
NOTE: Terminated at 50 to V_DDO/2.
NOTE 1: XTAL_IN can be overdriven by a single-ended LVCMOS signal. Please refer to Application Information section.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V_DDO/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: See phase noise plot.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
Table 6B. AC Characteristics, V_DD = V_DDO = 2.5V ± 5%, T_A = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
f_MAX
odc
Using External Crystal
Output Frequency _{Using External Clock}
Source NOTE 1
Output Duty Cycle
10
40
MHz
DC
100
MHz
47
53
%
tsk(o) Output Skew; NOTE 2, 3
80
ps
tjit
RMS Phase Jitter (Random); NOTE 4
25MHz, Integration Range:
100Hz – 1MHz
0.26
ps
t_R / t_F
t_EN
Output Rise/Fall Time
Output Enable
Time; NOTE 5
ENABLE1
ENABLE2
20% to 80%
200
800
ps
4
cycles
4
cycles
t_DIS
Output Disable
Time; NOTE 5
ENABLE1
ENABLE2
4
cycles
4
cycles
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
NOTE: All parameters measured at ƒ  f_MAX using a crystal input unless noted otherwise.
NOTE: Terminated at 50 to V_DDO/2.
NOTE 1: XTAL_IN can be overdriven by a single-ended LVCMOS signal. Please refer to Application Information section.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V_DDO/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: See phase noise plot.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
©2016 Integrated Device Technology, Inc.
7
Revision C September 28, 2016