82V3001A Datasheet, PDF (7/28 Pages) Integrated Device Technology – WAN PLL WITH SINGLE REFERENCE INPUT

IDT82V3001A
2
PIN DESCRIPTION
WAN PLL WITH SINGLE REFERENCE INPUT
Table - 1 Pin Description
Name
Type
Pin
Number
Description
V_SS
V_DDA
Power
Power
12, 18, 27, Ground.
38, 47 0 V. All V_SS pins should be connected to the ground.
37, 48
3.3 V Analog Power Supply.
Refer to Chapter 3.9 Power Supply Filtering Techniques.
V_DDD
Power
13, 19, 26
3.3 V Digital Power Supply.
Refer to Chapter 3.9 Power Supply Filtering Techniques.
OSCo
(CMOS) O
49
Oscillator Master Clock.
This pin is left unconnected.
OSCi
(CMOS) I
50
Oscillator Master Clock.
This pin is connected to a clock source.
Fref
I
F_sel1
I
Reference Input.
5 This is the input reference source (falling edge) used for synchronization. One of three possible frequencies (8 kHz, 1.544
MHz, or 2.048 MHz) may be used. The Fref pin is internally pulled up to V_DDD.
Input Frequency Select 1.
10 This input, in conjunction with F_sel0, determines which of three possible frequencies (8 kHz, 1.544 MHz, or 2.048 MHz )
may be input to the Reference Input.
F_sel0
I
9
Input Frequency Select 0.
See above.
MODE_sel1
I
Mode/Control Select 1.
2
This input, in conjunction with MODE_sel0, determines the operation mode of the IDT82V3001A (Normal, Holdover or
Freerun) . The logic level at this input is gated in by the rising edge of F8o. This pin is internally pulled down to V_SS. See
Table - 2.
MODE_sel0
I
RST
I
1
Mode/Control Select 0.
See above. The logic level at this input is gated in by the rising edge of F8o. This pin is internally pulled down to V_SS.
Reset Input.
4
A logic low at this pin resets the IDT82V3001A. To ensure proper operation, the device must be reset after the frequency
of the input reference is changed and power-up. The RST pin should be held low for a minimum of 300 ns. While the RST
pin is low, all framing and clock outputs are at logic high.
TCLR
I
TIE_en
I
FLOCK
I
TIE Circuit Reset.
3 Logic low at this input resets the TIE (Time Interval Error) control block, resulting in a realignment of output phase with
input phase. The TCLR pin should be held low for a minimum of 300 ns. This pin is internally pulled up to V_DDD.
TIE Enable.
56 A logic high at this pin enables the TIE control block while a logic low at this pin disables the TIE control block. The logic
level at this input is gated in by the rising edge of F8o. This pin is internally pulled down to V_ss.
45
Fast Lock Mode.
Set high to allow the DPLL to quickly lock to the input reference (less than 500 ms locking time).
LOCK
(CMOS) O
44
Lock Indicator.
This output goes high when the DPLL is frequency locked to the input reference.
HOLDOVER (CMOS) O
52
Holdover Indicator.
This output goes to a logic high whenever the DPLL goes into Holdover Mode.
NORMAL (CMOS) O
46
Normal Indicator.
This output goes to a logic high whenever the DPLL goes into Normal Mode.
FREERUN (CMOS) O
51
Freerun Indicator.
This output goes to a logic high whenever the DPLL goes into Freerun Mode.
PIN DESCRIPTION
7
November 14, 2012