5962-3829409MZA Datasheet, PDF (7/10 Pages) Integrated Device Technology – CMOS Static RAM 64K (8K x 8-Bit)

IDT7164S/L
CMOS Static RAM 64K (8K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
Timing Waveform of Read Cycle No. 1⁽¹⁾
tRC
ADDRESS
OE
CS2
CS1
DATAOUT
tAA
tOE
tOLZ ⁽⁵⁾
tACS2
tCLZ2(5)
tACS1
tCLZ1(5)
tOH
tCHZ2 ⁽⁵⁾
DATA VALID
tOHZ ⁽⁵⁾
tCHZ1 ⁽⁵⁾
Timing Waveform of Read Cycle No. 2^(1,2,4)
tRC
2967 drw 05
ADDRESS
DATAOUT
tAA
tOH
Timing Waveform of Read Cycle No. 3^(1,3,4)
CS1
tOH
DATA VALID
2967 drw 06
CS2
DATAOUT
POWER ICC
SUPPLY
CURRENT ISB
tACS2
tCLZ2 ⁽⁵⁾
tACS1
tCLZ1 ⁽⁵⁾
tPU
NOTES:
1. WE is HIGH for Read cycle.
2. Device is continuously selected, CS1 is LOW, CS2 is HIGH.
3. Address valid prior to or coincident with CS1 transition LOW and CS2 transition HIGH.
4. OE is LOW.
5. Transition is measured ±200mV from steady state.
6.742
DATA VALID
tCHZ2 ⁽⁵⁾
tCHZ1 ⁽⁵⁾
tPD
2967 drw 07