IDT82V3285 Datasheet, PDF (64/147 Pages) Integrated Device Technology – WAN PLL

IDT82V3285
WAN PLL
PHASE_ALARM_TIME_OUT_CNFG - Phase Lock Alarm Time-Out Configuration
Address: 08H
Type: Read / Write
Default Value: 00110010
7
6
5
4
3
2
1
0
MULTI_FACTO MULTI_FACTO TIME_OUT_VA TIME_OUT_VA TIME_OUT_VA TIME_OUT_VA TIME_OUT_VA TIME_OUT_VAL
R1
R0
LUE5
LUE4
LUE3
LUE2
LUE1
UE0
Bit
Name
Description
These bits determine a factor which has a relationship with a period in seconds. A phase lock alarm will be raised if the T0
selected input clock is not locked in T0 DPLL within this period. If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, the
phase lock alarm will be cleared after this period (starting from when the alarm is raised). Refer to the description of the
7-6
MULTI_FACTOR[1:0]
TIME_OUT_VALUE[5:0] bits (b5~0, 08H).
00: 2 (default)
01: 4
10: 8
11: 16
These bits represent an unsigned integer. If the value in these bits is multiplied by the value in the MULTI_FACTOR[1:0]
bits (b7~6, 08H), a period in seconds will be gotten.
5-0
TIME_OUT_VALUE[5:0] A phase lock alarm will be raised if the T0 selected input clock is not locked in T0 DPLL within this period. If the
PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, the phase lock alarm will be cleared after this period (starting from when the
alarm is raised).
Programming Information
64
December 9, 2008